Optimization of multi-channel BCH error decoding for common cases

Abstract

Error correcting systems have put increasing demands on system designers, both due to increasing error correcting requirements and higher throughput targets. These requirements have led to greater silicon area, power consumption and have forced system designers to make trade-offs in Error Correcting Code (ECC) functionality. Solutions to increase the efficiency of ECC systems are very important to system designers and have become a heavily researched area.Many such systems incorporate the Bose-Chaudhuri-Hocquenghem (BCH) method of error correcting in a multi-channel configuration. BCH is a commonly used code because of its configurability, low storage overhead, and low decoding requirements when compared to other codes. Multi-channel configurations are popular with system designers because they offer a straightforward way to increase bandwidth. The ECC hardware is duplicated for each channel and the throughput increases linearly with the number of channels. The combination of these two technologies provides a configurable and high throughput ECC architecture.This research proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. In this thesis, I examine how error frequency effects the utilization of BCH hardware. Rather than implement each decoder as a single pipeline of independent decoding stages, the channels are considered together and served by a pool of decoding stages. Modified hardware blocks for handling common cases are included and the pool is sized based on an acceptable, but negligible decrease in performance. i This thesis's experimental approach examines multi-channel configurations found in typical NAND flash systems. My experimental data shows that the proposed pooled group approach requires significantly fewer hardware blocks than a traditional multi-channel configuration. By allowing a 2% performance degradation and sizing the decoding pool appropriately, the scheme reduces hardware area by 47%-71% and dynamic power by 44%-59%.Additionally, I examined what improvements were possible with the improved design using the same hardware area as the traditional implementation. My experiments show that an improved throughput of 3x-5x can be achieved or NAND flash lifetime can be extended by 1.4x-4.5x. Dr. Shrivastava has provided invaluable input into both my research and my writing.