A high-performance concatenated BCH code and its hardware architecture for 100 Gb/s long-haul optical communications

Abstract

Abstract-This paper presents a six-iteration concatenated BoseChaudhuri-Hocquenghem (BCH) code and its high-speed twoparallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed six-iteration concatenated BCH code structure with a block interleaving methods allows the decoder to achieve 9.19 dB net coding gain performance at 10 -15 decoder output bit error rate to compensate for serious transmission quality degradation. Also, the proposed high-speed concatenated BCH decoder architecture was implemented to support 100 Gb/s data processing rate. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s longhaul optical communications.

A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture

“…Very few detailed reports of decoder implementations for OTN hard-decision FEC schemes can be found in the literature. To the best of our knowledge, [1] is the most recent: the considered FEC scheme uses a modified product-like concatenation of long BCH codes, resulting in a code length of almost 4 million bits and a code rate of 0.933. At a BER of 10 −15 , [1] has an NCG of 9.19 dB, against the 9.52 dB gained by our scheme (see Table I).…”

“…To the best of our knowledge, [1] is the most recent: the considered FEC scheme uses a modified product-like concatenation of long BCH codes, resulting in a code length of almost 4 million bits and a code rate of 0.933. At a BER of 10 −15 , [1] has an NCG of 9.19 dB, against the 9.52 dB gained by our scheme (see Table I). It achieves a throughput of 110 Gb/s with a latency of 38 µs, while our decoder reaches 100 Gb/s with a 319 ns latency.…”

“…It achieves a throughput of 110 Gb/s with a latency of 38 µs, while our decoder reaches 100 Gb/s with a 319 ns latency. The decoder in [1] has been synthesized in 90 nm CMOS technology, and yields a gate count of 3732 kgates at 430 MHz, not including SRAM, against the 1155 kgates of the decoder proposed in this work. Moreover, our decoder only uses registers, no SRAM, and the area these registers occupy is included in the gate count.…”

“…To achieve such low BER requirements, powerful Forward Error Correction (FEC) schemes must be employed. Recent approaches to high-performance, high-speed errorcorrection schemes follow one of two paths: concatenation of (often algebraic) hard-decision codes [1]- [3] or soft-decision, iterative decoding of inherently more powerful codes, first among all, Low-Density Parity-Check (LDPC) codes [4]. The latter produced high-gain FEC schemes, that however must rely on complex decoding architectures [5]- [8].…”

“…While no decoder architecture is proposed, the estimated latency of the decoding scheme is of 1.15 million bits. With similar overhead, the FEC proposed in [1] uses different BCH codes in a quasiproduct structure, achieving high throughput and a 9.19 dB NCG at a high cost in area occupation. The BCH-based product code proposed in [10], with a code length of 98 kbits bits and rate of 0.937, achieves a 9.4 NCG at BER=10 −15 , without implementation details.…”