1000 and 1500 volts planar devices using field plate and semi-resistive layers: design and fabrication

Abstract

An improved high-voltage technique based on the use of a field plate combined with semi-resistive layers (SrpOS) on oxide is proposed. The field plate and SIPOS are shown to have complementary functions. Junction curvature electric field effects are reduced by the presence of the field plate. The silicon surface potential is linearized by a primary SIPOS layer on oxide, thereby reducing the peak electric field at the edge of the field plate. A second highresistivity SIPOS layer provides an excellent passivation. The use of SIPOS as both a field-linearizing film and passivation permits completion of all chemical vapour depositions in a single reactor run. The following describes the complete design and fabrication of high-voltage (lo00 and 1500 V) planar transistors.

A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

“…Hence, in terms of a trade-off between BV and I RFP , ρ RFP is selected to be 1×10 9 •cm. Moreover, the contacts between RFP and the electrodes should be noticed [33]. There usually is a difference between the simulation and the realistic situation in the metallization effect [34].…”