The oxidation enhanced diffusion and oxidation stacking faults are assumed to be brought about by a self-interstitial supersaturation in the silicon. In such a case, supersaturation is related to the stresses present in the oxide and in the silicon during oxidation. The detailed analysis of the evolution of these stresses is conducted in relation to time, temperature and the nature of the oxidizing atmosphere, taking into account the viscous relaxation in the oxide. The silicon interstitial concentration during oxidation is directly linked with the stress in the silicon. This stress, which is a function of the stress evolution in the oxide enables us to describe qualitatively the experimental behavior of OED and OSF. However, quantitative analysis of stresses in silicon gives values insufficient to lead to a non-negligible self-interstitials concentration.
An eflicient junction termination technique for 4kV devices is presented. The complementarity of a field plate and a semi-resistive layer is shown allowing us to fabricate planar devices with a very high breakdown voltage and to decrease the silicon area consumed. The dynamic behaviour of SIPOS terminated diodes is physically explained and modelled. A solution to improve the dynamic behaviour up to 3000V/ps is proposed. The following describes the complete design, electrical characteristics and fabrication of 4kV planar diodes.
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