Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-semiconductor field-effect-transistor application It has been demonstrated that the presence of oxide monolayers in semiconductor surfaces alters the electronic potential at surfaces and, consequently, can drastically affect the electronic transport features of a practical device such as a field effect transistor. In this work experimental and theoretical approaches to characterize Al/germanium nanowire Schottky devices by using samples covered with a thin oxide layer (2 nm width) were explored. It was also demonstrated that the oxide layer on Ge causes a weak dependence of the metal work function on Schottky barrier heights indicating the presence of Fermi level pinning. From theoretical calculations the pinning factor S was estimated to range between 0.52 and 0.89, indicating a weak Fermi level pinning which is induced by the presence of charge localization at all nanowires' surface coming from interface states. V C 2013 AIP Publishing LLC. [http://dx.

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The performance of GaN-on-Silicon electronic devices is severely degraded by the presence of a parasitic conduction pathway at the nitride-substrate interface which contributes to switching losses and lower breakdown voltages. The physical nature of such a parasitic channel and its properties are however, not well understood. We report on a pronounced thickness dependence of the parasitic channel formation at AlN/Si interfaces due to increased surface acceptor densities at the interface in silicon. The origin of these surface acceptors is analyzed using secondary ion mass spectroscopy measurements and traced to thermal acceptor formation due to Si-O-N complexes. Low-temperature (5 K) magneto-resistance (MR) data reveals a transition from positive to negative MR with increasing AlN film thickness indicating the presence of an inversion layer of electrons which also contributes to parasitic channel formation but whose contribution is secondary at room temperatures.

The integration of MOCVD grown group III-A nitride device stacks on Si (111) substrates is critically dependent on the quality of the first AlN buffer layer grown. A Si surface that is both oxide-free and smooth is a primary requirement for nucleating such layers. A single parameter, the AlN layer growth stress, is shown to be an early (within 50 nm), clear (<0.5 GPa versus >1 GPa) and fail-safe indicator of the pre-growth surface, and the AlN quality required for successful epitaxy. Grain coalescence model for stress generation is used to correlate growth stress, the AlN-Si interface and crystal quality.

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A low-temperature (∼250 °C) high-pressure oxidation technique is used for the thermal oxidation of gallium arsenide in an ambient of oxygen and water vapor. It is shown that a uniform and chemically stable oxide with high band-gap energy can be grown on GaAs by this process. The role of water vapor and oxygen is studied in detail to obtain information on the oxidation mechanism. The electrical characteristics and the composition of this oxide are presented to demonstrate its suitability for surface passivation and metal-oxide–semiconductor devices.