0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier

Cabrera-Bernal, Elena; Pennisi, S.; Grasso, Alfio Dario; Torralba, A.; Carvajal, R.G.

doi:10.1109/tcsi.2016.2597440

Cited by 111 publications

(40 citation statements)

References 33 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Our proposed OTA has the highest gain (due to cascading of the three stages) and highest phase margin (theoretically, it should be 90°, but cascading creates additional poles, not accounted for in the model). It has the second best small‐signal FOM and IFOM after, 18 which however has less than half the gain. Its large‐signal FOM is significantly lower than, 18 but only marginally lower than, 15,17 which also have less than half the gain.…”

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

“…It has the second best small‐signal FOM and IFOM after, 18 which however has less than half the gain. Its large‐signal FOM is significantly lower than, 18 but only marginally lower than, 15,17 which also have less than half the gain. The proposed OTA can be sized to operate with a much larger load capacitor, provided that the compensation capacitors are scaled: this would not change the FOMs because it would trade‐off bandwidth for load capacitance but would increase the phase margin (which would be closer to the theoretical 90° of a single‐pole amplifier), because the parasitic poles of the cascode stages would be less relevant.…”

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

See 1 more Smart Citation

An improved reversed miller compensation technique for three‐stage CMOS OTAs with double pole‐zero cancellation and almost single‐pole frequency response

Centurelli

Monsurrò

Scotti

et al. 2020

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary This paper presents an improved reversed nested Miller compensation technique exploiting a single additional feed‐forward stage to obtain double pole‐zero cancellation and ideally single‐pole behavior, in a three‐stage Miller amplifier. The approach allows designing a three‐stage operational transconductance amplifier (OTA) with one dominant pole and two (ideally) mutually cancelling pole‐zero doublets. We demonstrate the robustness of the proposed cancellation technique, showing that it is not significantly influenced by process and temperature variations. The proposed design equations allow setting the unity‐gain frequency of the amplifier and the complex poles' resonance frequency and quality factor. We introduce the notion of bandwidth efficiency to quantify the OTA performance with respect to a telescopic cascode OTA for given load capacitance and power consumption constraints and demonstrate analytically that the proposed approach allows a bandwidth efficiency that can ideally approach 100%. A CMOS implementation of the proposed compensation technique is provided, in which a current reuse scheme is used to reduce the total current consumption. The OTA has been designed using a 130‐nm CMOS process by STMicroelectronics and achieves a DC gain larger than 120 dB, with almost single‐pole frequency response. Monte Carlo simulations have been performed to show the robustness of the proposed approach to process, voltage, and temperature (PVT) variations and mismatches.

show abstract

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

An improved reversed miller compensation technique for three‐stage CMOS OTAs with double pole‐zero cancellation and almost single‐pole frequency response

Centurelli

Monsurrò

Scotti

et al. 2020

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…The second stage of the amplifier is formed by the transistor M 6 , loaded with the current source based on the transistor M 5 . The output stage (M 7 -M 10 ) [16], [20] operates in class AB, that increases its current driving capability and SR. The capacitances C C1 and C C2 are used for frequency compensation.…”

Section: Circuit Descriptionmentioning

confidence: 99%

A 0.3-V 98-dB Rail-to-Rail OTA in $0.18~\mu$ m CMOS

Kulej

Khateb

2020

IEEE Access

View full text Add to dashboard Cite

A new solution for an ultra-low-voltage, ultra-low-power operational transconductance amplifier (OTA) is presented in the paper. The design exploits a three-stage structure with a Reversed Miller Compensation Scheme, where the input stage is based on a non-tailed bulk-driven differential pair. Optimization of the structure for very low supply voltage is discussed. The resulting amplifier outperforms other ultra-low-voltage OTAs in terms of a DC voltage gain and power efficiency, expressed by standard figures of merit. Experimental verification using a 0.18 µm CMOS technology, with supply voltage of 0.3-V, showed a dissipation power of 13 nW, a DC voltage gain of 98 dB, a gain-bandwidth product of 3.1 kHz and an average slew-rate of 9.1 V/ms at 30 pF load capacitance. The experimental results agree well with simulations. INDEX TERMS Bulk-driven, operational transconductance amplifier, operational amplifier, low voltage, low power.

show abstract

“…It is apparent from Table 6 that the proposed OTA1 outperforms all other previously reported OTAs in terms of FOM SV , FOM L , and FOM LV . Regarding the FOM S , only 3 circuits 19,25,26 show similar or better performance. The OTA2 and OTA3 also offer one of the best FOMs, but their performance is worse due to the larger compensation capacitances C C , applied to overcome second-order effects.…”

Section: Comparisonmentioning

confidence: 99%

“…In recent years, a large number of LV BD OTAs have been reported in the literature. [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20] Considering these designs, we can conclude that the supply voltage for many truly differential OTAs with a gain-bandwidth product (GBW) ranging from 1 to 10 MHz is nearly constant and equal to around |V TH | + 0.3 V. Lower V DD (close to |V TH |) could be achieved for circuits biased with very low currents (at the cost of a lower GBW), 7,14 or for circuits with pseudo-differential input stages. 6,16 Therefore, many papers are focused on overcoming the disadvantages of the BD technique rather than further decreasing the supply voltage.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

Kulej

Khateb

2018

Circuit Theory & Apps

View full text Add to dashboard Cite

A family of bulk-driven CMOS operational transconductance amplifiers (OTAs) has been designed for extremely low supply voltages (0.3-0.5 V). Three OTA design schemes with different gain boosting techniques and class AB input/output stages are discussed. A detailed comparison among these schemes has been presented in terms of performance characteristics such as voltage gain, gain-bandwidth product, slew rate, circuit sensitivity to process/mismatch variations, and silicon area. The design procedures for all the compared structures have been developed. The OTAs have been fabricated in a standard 0.18-μm n-well CMOS process from TSMC. Chip test results are in good agreement with theoretical predictions and simulations.

show abstract

0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier

Cited by 111 publications

References 33 publications

An improved reversed miller compensation technique for three‐stage CMOS OTAs with double pole‐zero cancellation and almost single‐pole frequency response

An improved reversed miller compensation technique for three‐stage CMOS OTAs with double pole‐zero cancellation and almost single‐pole frequency response

A 0.3-V 98-dB Rail-to-Rail OTA in $0.18~\mu$ m CMOS

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

Contact Info

Product

Resources

About