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All-GaN integrated cascode heterojunction field effect transistors were designed and fabricated for power switching applications. A threshold voltage of +2 V was achieved using a fluorine treatment and a metal-insulator-semiconductor gate structure on the enhancement mode part. The cascode device exhibited an output current of 300 mA/mm by matching the current drivability of both enhancement and depletion mode parts. The optimisation was achieved by shifting the threshold voltage of the depletion mode section to a more negative value with the addition of a dielectric layer under the gate. The switching performance of the cascode was compared to the equivalent GaN enhancement-mode-only device by measuring the hard switching speed at 200 V under an inductive load in a double pulse tester. For the first time, we demonstrate the switching speed advantage of the cascode over equivalent GaN enhancement-mode-only devices, due to the reduced Miller-effect and the unique switching mechanisms. These observations suggest that practical power switches at high power and high switching frequency will benefit as part of an integrated cascode configuration.

We have demonstrated enhancement mode operation of AlInN/GaN (MIS)HEMTs on Si substrates using the fluorine plasma implant technique. The plasma RF power and treatment time was optimized to prevent the penetration of the fluorine into the channel region to maintain high channel conductivity and transconductance. An analysis of the threshold voltage was carried out which defined the requirement for the fluorine sheet concentration to exceed the charge at the dielectric/AlInN interface to achieve an increase in the positive threshold voltage after deposition of the dielectric. This illustrates the importance of control of both the plasma conditions and the interfacial charge for a reproducible threshold voltage. A positive threshold voltage of +3V was achieved with a maximum drain current of 367 mA/mm at a forward gate bias of 10V.

Effects of surface plasma treatment on threshold voltage hysteresis and instability in metal-insulatorsemiconductor (MIS) AlGaN/GaN heterostructure HEMTsControl of leakage currents in the buffer layers of GaN based transistors on Si substrates is vital for the demonstration of high performance devices. Here, we show that the growth conditions during the metal organic chemical vapour deposition growth of the graded AlGaN strain relief layers (SRLs) can significantly influence the vertical leakage. Using scanning capacitance microscopy, secondary ion mass spectrometry, and transmission electron microscopy, we investigate the origins of leakage paths and show that they result from the preferential incorporation of oxygen impurities on the side wall facets of the inverted hexagonal pyramidal pits which can occur during the growth of the graded AlGaN SRL. We also show that when 2D growth of the AlGaN SRL is maintained a significant increase in the breakdown voltage can be achieved even in much thinner buffer layer structures. These results demonstrate the importance of controlling the morphology of the high electron mobility transistor buffer layer as even at a very low density the leakage paths identified would provide leakage paths in large area devices.

The band alignments of sputtered ZrO2, Al2O3 and MgO on GaN have been measured experimentally using x-ray photoelectron spectroscopy (XPS). The valence band offsets (±0.2 eV) for ZrO2, Al2O3 and MgO on GaN using Kraut’s method and charge-corrected XPS core levels were found to be 0.4 eV, 1.1 eV and 1.2 eV with corresponding conduction band offsets (±0.2 eV) of 1.3 eV, 2.0 eV and 2.8 eV, respectively. The electrical characterization of metal insulator semiconductor (MIS)-capacitors with different gate dielectrics (ZrO2, Al2O3 and MgO) has been performed as well. The current density of the MIS-capacitors with gate dielectrics MgO and Al2O3 at a positive bias of 1 V show lower leakage currents of 3.2  ×  10−6 A cm−2 and 5.3  ×  10−6 A cm−2 respectively, whereas, the MIS-capacitors with ZrO2 gate dielectric have the highest leakage current of 6.2  ×  10−4 A cm−2 at 1 V.

This is a repository copy of Enhancement-mode metal-insulator-semiconductor GaN/AlInN/GaN heterostructure field-effect transistors on Si with a threshold voltage of +3.0V and blocking voltage above 1000V. White Rose Research Online URL for this paper: http://eprints.whiterose.ac.uk/98678/ Version: Accepted Version Article: Lee, K.B., Guiney, I., Jiang, S. et al. (7 more authors) (2015) Enhancement-mode metal-insulator-semiconductor GaN/AlInN/GaN heterostructure field-effect transistors on Si with a threshold voltage of +3.0V and blocking voltage above 1000V. Applied Physics Express, 8 (3). 036502. Enhancement-mode AlInN/GaN metal-insulator-semiconductor heterostructure field effect transistors on silicon substrates are reported. The fabricated devices exhibit a threshold voltage of +3V using a fluorine-based plasma treatment technique and gate dielectric. A drain current density of 295mA/mm at a gate bias of +10V is measured. An excellent off-state blocking voltage capability of 630V at leakage current of 1µA/mm and more than 1000V at 10µA/mm is achieved on a device with 20µm gate-drain separation at gate bias of 0V. The dynamic on-resistance is ~2.2 times the DC on-resistance when pulsing from off-state drain bias of 500V.

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In a bid to understand the commonly observed hysteresis in the threshold voltage (V TH) in AlGaN/GaN MISHEMTs during forward gate bias stress, we have analyzed a series of measurements on devices with no surface treatment and with two different plasma treatments before the in-situ Al 2 O 3 deposition. The observed changes between samples were quasi