Operation of a static. current mode logic (CMZ)fiequency divider to clock frequencies exceeding ISOGHz is reported. The divide-by-8 circuit described here has been realized in a highly scaled 0 . 4~ InP/lnGaAs/InP DHBT technolop, dissipaies only 45mW per laich. and achieves this using purely resistive loads. Thermal limitations in device performance are observed to play a key role, demonstrating the need for aggressive heat management in high speed technologies On a&// thickness wafer in a 27°C ambieni, the maximum operating frequency a/ the divider was 143.6GHz; fhis range errended to ISI.2GHr when an air Jaw at -3OOC was ertablishedacross the wafer.
INTRODUCTIONThe frequency agility available from direct digital synthesis (DDS) makes it an attractive circuit technique for generating advanced microwave and millimeter wave radar and communication signals. However, DDS at microwave frequencies represents a significant technological challenge because it requires clock rates 2.5-3 times the maximum synthesized frequency. There are typically 4-6 gate delays per clock cycle so a simple flip-flop must have a maximum toggle rate 10-15 times the synthesized frequency. Realization of IOGHz signals thus requires flip-flops with toggle rates in the range of 100-150GHz [I]. Unlike multiplexer or demultiplexer circuits, which typically require only one or two flip-flops to operate at the maximum clock rate, DDS circuits require that much larger fractions of the circuit operate at speed. The speed and gate-count requirements taken together lead to the selection of a logic family with extremely high-speed and low power dissipation per gate for these applications. Among the candidate technologies, the highest toggle rates
A completely integrated single-chip phase locked loop based on a 0.2p.m gate length enhancement / depletion AlGaAs / CaAs / AIGaAs-HEMT technology has been designed and characterized. The chip contains a VCO with 34 CHz center frequency, a dynamic frequency divider by two, a static divider by eight, a phase detector, and a loop filter. The chip size is 2.0 x 1.5 mmz. The power consumption is 7.2 W at a supply voltage of -5.0 V. The locking range is approximately f 700 MHz.
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