20-40 Gb/s 0.2-/spl mu/m GaAs HEMT chip set for optical data receiver

Notice of Violation of IEEE Publication Principles - A Low Power 12.5Gb/s SiGe Limiting Amplifier Using a Feed-forward Adjustable Threshold Loss-Of-Signal Detector

“…This results in smaller current consumption in the offset loop, which in many designs constitute a significant percentage of the overall IC power consumption [1][2][3][4][5]. Two feedforward capacitors Cff were used to add a zero in the signal path, which cancels the pole introduced by the Roff resistors.…”

“…Most existing 1OGb/s limiting amplifiers use the Cherry-Hooper (CH) gain stage due to its high bandwidth efficiency, at the expense of larger power dissipation and higher circuit complexity [1][2][3][4][5][6]. This architecture is optimal for 1OGb/s ICs realized in processes with relatively low transition frequency (fT=30 to 50GHz).…”

“…DC offset cancellation loops are usually used to minimize the output offset voltage. Passive [1][2][3] and active [4][5][6][7] offset cancellation loops were implemented in the past, their low cut-off frequency requiring off-chip compensation capacitors. Recently, a dual offset cancellation loop architecture was introduced to minimize the output offset voltage, while the Miller multiplication was used to integrate on-chip the compensation capacitors [7].…”

Notice of Violation of IEEE Publication Principles - A 12.5GHz SiGe BICMOS limiting amplifier using a dual offset cancellation loop

“…Most existing 10Gb/s limiting amplifiers use the Cherry-Hooper wideband amplifier as their main gain stage in the data signal path [1][2][3][4][5]. Its main advantage is a high bandwidth (f T /3…f T /5), which allows the achievement of 10Gb/s operation even in processes with moderate transition frequencies (f T =40-60GHz).The price paid for the large bandwidth is a higher circuit complexity and a larger power dissipation.…”

“…To minimize the pulse-width distortion a DC offset cancellation loop need to be used. Passive offset cancellation loops were used in the past [1,2], achieving moderate output offset voltages (several mV). To further reduce the output offset voltage active DC offset cancellation loops have been implemented [3][4][5][6].…”