A low power (45mW/latch) static 150GHz CML divider

Abstract

Operation of a static. current mode logic (CMZ)fiequency divider to clock frequencies exceeding ISOGHz is reported. The divide-by-8 circuit described here has been realized in a highly scaled 0 . 4~ InP/lnGaAs/InP DHBT technolop, dissipaies only 45mW per laich. and achieves this using purely resistive loads. Thermal limitations in device performance are observed to play a key role, demonstrating the need for aggressive heat management in high speed technologies On a&// thickness wafer in a 27°C ambieni, the maximum operating frequency a/ the divider was 143.6GHz; fhis range errended to ISI.2GHr when an air Jaw at -3OOC was ertablishedacross the wafer. INTRODUCTIONThe frequency agility available from direct digital synthesis (DDS) makes it an attractive circuit technique for generating advanced microwave and millimeter wave radar and communication signals. However, DDS at microwave frequencies represents a significant technological challenge because it requires clock rates 2.5-3 times the maximum synthesized frequency. There are typically 4-6 gate delays per clock cycle so a simple flip-flop must have a maximum toggle rate 10-15 times the synthesized frequency. Realization of IOGHz signals thus requires flip-flops with toggle rates in the range of 100-150GHz [I]. Unlike multiplexer or demultiplexer circuits, which typically require only one or two flip-flops to operate at the maximum clock rate, DDS circuits require that much larger fractions of the circuit operate at speed. The speed and gate-count requirements taken together lead to the selection of a logic family with extremely high-speed and low power dissipation per gate for these applications. Among the candidate technologies, the highest toggle rates

A 1.2V 15.6mW 81GHz 2:1 Static CML Frequency Divider with a Band-Pass Load in a 90nm SOI CMOS Technology

“…The draw back of the slab inductor load is a significant area penalty. As shown in Table I, we also report a divider core power in this work more than 83 to 97% lower than state of the art compound semi-conductor, for a self-oscillation frequency only 27% lower [8]. The self-oscillation frequency is a more accurate way of comparing divider speed, since the maximum operating frequency depends of how much power can be provided at the circuit input transistor.…”

172 GHz divide-by-two circuit using a 0.25-µm InP HBT technology

“…InP bipolar transistors can achieve higher bandwidth than Si devices with less aggressive scaling and much simpler fabrication processes. Recent InP DHBT technologies have demonstrated remarkable high-speed performance from transistors with submicron features achieving 560 GHz f T and f max [3] and divider operation in the 150 GHz range [4,5,6]. Unlike CMOS processes predicted to face fundamental challenges beyond the 22-nm generation, the InP DHBT technologies have been far from their scaling limits.…”

An Ultra Low-Power (⩽13.6 mW/latch) Static Frequency Divider in an InP/InGaAs DHBT Technology

“…Because M-S flip-flops are utilized as retiming elements for data synchronization, their maximum toggle rate often sets a limit for circuit bandwidth. Amongst the aforementioned processes, static frequency dividers with an operating f clk > 150 GHz [2], [3], [5], [6] have been demonstrated. The flip-flop operating power associated with these circuits varies from 400 to 600 mW, with a corresponding power-delay product of ∼ 800 fJ/latch.…”