Articles you may be interested inHigh breakdown voltage in AlN/GaN metal-insulator-semiconductor high-electron-mobility transistors J. Vac. Sci. Technol. B 32, 051204 (2014); 10.1116/1.4891966GaN metal-insulator-semiconductor high-electron-mobility transistor with plasma enhanced atomic layer deposited AlN as gate dielectric and passivation

Enhancement-mode (E-mode) AlGaN/GaN HEMTs are attracting interest because their use of a single-polarity voltage supply simplifies power amplifier circuits. Several approaches have been applied to develop E-mode AlGaN/GaN HEMTs [1] [2], but thus far, the performance of these devices has been limited. In this report, we describe a gate recess technique, based on SiCl 4 plasma etching, to achive leakage reduction. The proposed gate recess process plays an important role in obtaining Emode operation in an AlGaN/GaN HEMT. On the other hand, we previously applied a highly resistive low-temperature GaN (LT-GaN) cap layer to serve as a gate insulator and provide surface passivation in AlGaN/GaN HEMTs, and we found that this approach can suppress gate leakage and current collapse [3]. By combining these approaches, using both the proposed gate recess process and an LT-GaN cap layer, we fabricated E-mode devices with high-performance characteristics, including a high transconductance, a high drain current, a high breakdown voltage (BV off ), and a low gate leakage current. Figure 1 shows a schematic cross section of a recessed gate LT-GaN/AlGaN/GaN HEMT. The ohmic contact electrodes were formed by rapid thermal annealing of Ti/Al/Ti/Au at 850 • C. For Schottky contact formation, the etching region was patterned with photoresist, and recess etching was carried out by ICP-RIE using SiCl 4 plasma to achieve a gate-to-channel distance of 10 nm. In the present work, the LT-GaN cap layer under the gate was removed during the recess etching process. Subsequently, a N 2 plasma treatment was applied to reduce the amount of nitrogen vacancy-related defects, and a buffered hydrofluoric acid (BHF) treatment was used to remove discharge-gas-related residues. After these posttreatments, Ni/Au metals were evaporated in a self-aligned process with respect to the etching region. For comparison, a conventional AlGaN/GaN HEMT without a LT-GaN cap layer was also fabricated, without using gate recess etching. The gate length of these devices was 0.6 µm, while the gate width was 50×2 µm. The source-to-gate distance was 1.0 µm, and the gate-to-drain distance was 3.0 µm. Figure 2 shows the transfer characteristics of the fabricated HEMTs. For the E-mode HEMT, the value of V th , determined as the gate bias intercept of the linear extrapolation of the drain current at the peak g m , was +0.51 V. The peak g m was 236 mS/mm, and I d reached 648 mA/mm at a V gs of 4 V without excessive gate leakage (I g = 0.82 mA/mm at V gs = 4 V). In addition, both the gate leakage current under a reverse bias and the gate current under a foward bias were significantly reduced in the E-mode HEMT as compared to the conventional HEMT, as illustrated in Figure 3. These results suggest that the dry etching process introduced deep accepters into the surface of the AlGaN barrier layer. As a result, the depletion layer thickness of the gate increased, and the gate leakage current due to electron tunneling became small. Figure 4 shows the DC and pulsed I d -V ds characteri...

Deep level electron traps in n-GaN grown by metal organic vapor phase epitaxy (MOVPE) on Si (111) substrate were studied by means of deep level transient spectroscopy (DLTS). The growth of n-GaN on different pair number of AlN/GaN superlattice buffer layers (SLS) system and on c-face sapphire substrate are compared. Three deep electron traps labeled E2 (the energy level is not clear), E4 (0.7-0.8 eV), E5 (1.0-1.1 eV), were observed in n-GaN on Si substrate. And the concentrations of these traps observed for n-GaN on Si are very different from that observed for n-GaN on sapphire substrate. E4 is the dominant of these levels for n-GaN on Si substrate, and it is not related to linear array defect like dislocation line, but it behaves like point-defect based on the analysis by electron capture kinetics, in spite of having high dislocation density to the order of 10 10 cm -2 .

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AlN/AlGaN/GaN MIS‐HEMTs were grown on 4 inch silicon to suppress the gate leakage and achieve high breakdown. However the drain current density maximum obtained is low (361 mA/mm) for 15 μm MIS‐HEMTs. Since the contact resistance of the Ohmic contacts on the insulating AlN is high (5.1 Ωmm), the thin AlN layer was etched prior to the evaporation of the source‐drain Ohmic contact. Though the recessed Ohmic contact reduced the contact resistance to 2.5 Ωmm there is no improvement in the drain current density. The poor quality of the 2 nm AlN growth on silicon could be the possible reason behind the low drain current density. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)