Charge-based capacitance measurement (CBCM) is used to implement an on-chip microelectrode biosensor combined with complementary metal oxide semiconductor (CMOS) circuitry. Electrical double-layer capacitance is exploited to measure the interfacial property changes during biorecognition events at electrode surfaces. A test chip with 4 Â 4 mm 2 planar electrodes and a differential capacitance-to-voltage conversion circuit was designed and fabricated using 1.2 mm CMOS technology. The chip was experimentally characterized in sodium chloride (NaCl) aqueous solutions to demonstrate its feasibility to detect capacitance variation when the ionic concentration is varied between 0.1 mM and 1 M over a wide frequency range. To show the feasibility of the microfabricated electrode for detecting biomaterials in such a small sensor area, the hybridization of 20-mer probe oligonucleotides in a phosphate-buffered solution was demonstrated. A 20% change in capacitance (10 fF) before and after the injection of complimentary target oligonucleotides is successfully observed, showing promise for future miniature yet high-throughput biosensor arrays.
The trend of health care screening devices in the world is increasingly towards the favor of portability and wearability. This is because these wearable screening devices are not restricting the patient’s freedom and daily activities. While the demand of low power and low cost biomedical system on chip is increasing in exponential way, the front-end electrocardiogram (ECG) amplifiers are still suffering from flicker noise for low frequency cardiac signal acquisition, 50Hz power line electromagnetic interference, and the large unstable input offsets due to the electrode-skin interface is not attached properly. In this paper, a CMOS based ECG amplifier that suitable for low power wearable cardiac screening is proposed. The amplifier adopts the highly stable folded cascode topology and later being implemented into RC feedback circuit for low frequency DC offset cancellation. By using 0.13µm CMOS technology from Silterra, the simulation results show that this front-end circuit can achieve a very low input referred noise of 1pV/Hz1/2 and high common mode rejection ratio of 174.05dB. It also gives voltage gain of 75.45dB with good power supply rejection ratio of 92.12dB. The total power consumption is only 3µW and thus suitable to be implemented with further signal processing and classification back end for low power wearable biomedical device.<br /><br />
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