Integrated Soil Monitoring System for Internet of Thing (IOT) Applications

Lau, Xin Yi; Soo, Chun Heng; Yusof, Yusmeeraz; Isaak, Suhaila

doi:10.1007/978-981-15-5281-6_50

Cited by 3 publications

(7 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to examine the core utilization of the proposed BIST, Integrated Circuit Complier (ICC) test was implemented. The constraint core utilization is set as 0.90 (ratio number, no unit) for best performance of power and area, which is similar reported by earlier findings iDAQ system without fault testing circuit using 180 nm CMOS Process [7]. The setup time (tS) and the hold time (tH) are simulated as 0.36 ns and 0.26 ns of the slack time.…”

Section: Physical Implementation Iccmentioning

confidence: 94%

“…The BIST module which is integrated with CUT schemes showed significant improvement of fault diagnosis by examine each CUT in sequence and is able to tolerate with signal verification to ensure all incoming signal can be processed. The ASIC performance comparison between the earlier iDAQ without BIST scheme [7] and with BIST scheme is tabulated in Table 2.…”

Section: Physical Implementation Iccmentioning

confidence: 99%

“…The same DAQ design which is implemented by Chong et. al [7] already tested using prototype circuit on De2-FPGA. However, this prototype circuit encountered with the error occurs due to the analog to digital signal conversion.…”

Section: Hardware Test Using Fpgamentioning

confidence: 99%

“…Hence, Chong et. al [7] work is improved by Chang et.al [6] using sparse KSA module with fault tolerance capability.…”

Section: Introductionmentioning

confidence: 99%

“…BIST scheme is explicitly performed as fault diagnosis method for integrated digital module such multiplier chain, embedded memory and bootstrapped switches [9]. However, there are few works or findings on the fault diagnosis schemes for photon counter accumulator circuit, specifically can test the normal count and false count [6], [7].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process

Isaak

Yeo

Chang

et al. 2022

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

This study investigated the use of a built-in-self-test (BIST) module detecting catastrophic errors in photon-counter accumulator for liquid contamination level measurement. Efficient algorithms are exceptionally demanded for a high-count rate and low voltage system photon counting circuit on-chip. The photon counter sensors are also required high sensitivity digital counter that encodes the arrival of photon in precise timing to prevent any count erroring the absence of light. The proposed BIST is integrated on the data acquisition system, where the accumulator is located. The design circuit, functionality and topology tests of BIST and circuit under test are realized with 180 nm Silterra CMOS Process. The same Verilog codes are verified using field programmable gate array (FPGA) to predict the hardware functionality prior fabrication. The measurement was able to detect at least 90 % fault coverage within 16-bit data acquisition system at minimum operating frequency of 166.7 MHz.

show abstract

Section: Physical Implementation Iccmentioning

confidence: 94%

Section: Physical Implementation Iccmentioning

confidence: 99%

Section: Hardware Test Using Fpgamentioning

confidence: 99%

“…Hence, Chong et. al [7] work is improved by Chang et.al [6] using sparse KSA module with fault tolerance capability.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%