A 32nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 μA/μm (n/p) are achieved at I off =100 nA/μm, V dd =1V, 30nm physical gate length and 130nm gate pitch. This technology also provides a high-Vt solution for high-performance low-power applications with its high drive currents of 1020/700 μA/μm (n/p) at total I off ~1 nA/μm @ V dd = 1V.Low sub-threshold leakage was achieved while successfully containing I boff and I goff well below 1nA/um. Ultra high density 0.15 um 2 SRAM cell is fabricated by high NA 193nm immersion lithography. Functional 2Mb SRAM test-chip in 32nm design rule has been demonstrated with a controllable manufacturing window.
This paper reports on the design and characterization of a low phase noise MEMS oscillator with ultra-low polarization voltage. An innovative oscillation circuitry is also proposed by a high gain-bandwidth, low-power TIVA (trans-impedance voltage amplifier) which is composed of two stages: the I-to-V stage and voltage gain stage. The TIVA is fabricated using 1P6M 0.18 m CMOS technology and has been demonstrated with gain of 110dBΩ, 3-dB bandwidth of 60MHz, and power consumption of only 5.9mW, achieving the highest figure of merit (FOM) among reported literatures. Moreover, the input referred noise is less than 2.5 pA/√Hz in the 10 kHz to 100 MHz range. In order to reduce the motional impedance of capacitive MEMS resonators, a 50 nm-gap process together with vacuum capping technology is implemented. The TIVA chip is wire-bonded to a 17.6-MHz high-Q (Q unloaded ~ 8,000) silicon-based capacitive MEMS resonator and perform the phase noise of -121 dBc/Hz @1kHz offset and -131 dBc/Hz @10kHz offset, respectively, at polarization voltage of 6.8V. At 2.5V polarization voltage, the phase noise can reach -116 dBc/Hz @1kHz offset and -125 dBc/Hz @10kHz offset, respectively.
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