This paper examines the edge direct tunneling (EDT) of electron from n + polysilicon to underlying n-type drain extension in off-state n-channel MOSFET's having ultrathin gate oxide thicknesses (1.4-2.4 nm). It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT), and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field OX at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates OX to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension. Once OX is known, an existing DT model readily reproduces EDT-consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.

Effects of oxygen addition and treating distance on cleaning organic contaminants on stationary and non-stationary (1-9 cm/s) ITO glass surfaces by a parallel-plate nitrogen-based dielectric barrier discharge (DBD) are investigated experimentally; the DBD is driven by a 60 kHz bipolar quasi-pulsed power source. The results show that two regimes of favorable operating condition for improving the hydrophilic property of the surface (reducing the contact angle from 84°to 25-30°) are found. The measured spatial distribution of NO-c UV emission, O 3 concentration and OES spectra are shown to strongly correlate with the measured hydrophilic property. At the near jet downstream locations (z \ 10 mm), the metastable N 2 ðA 3 P þ u Þ and photo-induced dissociation of ozone play dominant roles in cleaning the ITO glass surface; while at the far jet downstream locations (z [ 10 mm), where the ratio of oxygen to nitrogen is lower, only the long-lived metastable N 2 ðA 3 P þ u Þ plays a major role in cleaning the ITO glass surface.

A 32nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 μA/μm (n/p) are achieved at I off =100 nA/μm, V dd =1V, 30nm physical gate length and 130nm gate pitch. This technology also provides a high-Vt solution for high-performance low-power applications with its high drive currents of 1020/700 μA/μm (n/p) at total I off ~1 nA/μm @ V dd = 1V.Low sub-threshold leakage was achieved while successfully containing I boff and I goff well below 1nA/um. Ultra high density 0.15 um 2 SRAM cell is fabricated by high NA 193nm immersion lithography. Functional 2Mb SRAM test-chip in 32nm design rule has been demonstrated with a controllable manufacturing window.

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