Compressed sensing (CS) is a promising approach to the compression and reconstruction of electrocardiogram (ECG) signals. It has been shown that following reconstruction, most of the changes between the original and reconstructed signals are distributed in the Q, R, and S waves (QRS) region. Furthermore, any increase in the compression ratio tends to increase the magnitude of the change. This paper presents a novel approach integrating the near-precise compressed (NPC) and CS algorithms. The simulation results presented notable improvements in signal-to-noise ratio (SNR) and compression ratio (CR). The efficacy of this approach was verified by fabricating a highly efficient low-cost chip using the Taiwan Semiconductor Manufacturing Company’s (TSMC) 0.18-μm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The proposed core has an operating frequency of 60 MHz and gate counts of 2.69 K.
This paper presents a cost-effective, two-dimensional (2-D) discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) capable of MPEG1/2/4, H.264 4 × 4/8 × 8, and VC-1 4 × 4/8 × 8/4 × 8/8 × 4 standards. We developed multilevel factor sharing in conjunction with distributed arithmetic in a scheme referred to as common sharing distributed arithmetic to enable sharing of the coefficient matrix circuit and replace multipliers with adders and shifters. By taking advantage of the similarities between DCT and IDCT transforms, we were able to implement an interlaced sorting method in a single circuit of the DCT and IDCT transform core in order to reduce area overhead while enabling the simultaneous operation of DCT and IDCT. The proposed design arranges the data of the first dimension and second dimension in order to reuse the same 1-D core to compute 2-D data. In this manner, first dimension and second dimension data of DCT and IDCT can be processed simultaneously in a single transform core. The efficacy of the proposed approach has been verified by fabricating a test chip using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm complementary metal-oxide semiconductor process. The inverse transform core was shown to have an operating frequency of 227 MHz and throughput of 454 Mpel/s with a gate count of 32.5 k. Figure 4. Time scheduling of proposed SORT1 circuit for N = 8. 1st-D, first-dimensional; 2nd-D, seconddimensional; DCT, discrete cosine transform; IDCT, inverse discrete cosine transform. 1582 Y.-H. TSENG ET AL.
Cost-effective two-dimensional (2D) discrete cosine transform (DCT) and inverse DCT architectures capable of supporting multiple standards of MPEG, H.264 and VC-1 are presented. The proposed core utilises a 1D core and a transposed memory to achieve a low cost design. Multi-level factor share is implemented in conjunction with distributed arithmetic in a system to enable the sharing of the coefficient matrix circuit in order to reduce hardware costs. The proposed approach employs a time-distribution scheme to enable the simultaneous processing of the first and second dimensions to enhance throughput. A high efficiency of this approach was verified by fabricating a test chip using the TSMC 0.18 μm CMOS process. The architecture has an operating frequency of 200 MHz, and throughput of 800 M-pixels/s with a gate count of 44.5 K.Introduction: Video compression is widely used in applications such as video conferences, mobile video, and digital television. A variety of transform dimensions and coefficients have been developed by the International Organization for Standardization (ISO), the International Telecommunication Union Telecommunication Standardization Sector (ITU-T), and Microsoft Corporation.Discrete cosine transform (DCT) and its inverse DCT (IDCT) are the transforms most widely used in image and video compression applications due to good energy compaction. The most important issues related to DCT and IDCT transform cores are area efficiency and data throughput, and numerous novel DCT/IDCT architectures have been introduced to deal with these issues [1][2][3][4][5]. The high-speed 2D transform architecture with unique kernel for multi-standard video applications was proposed in [1]. That architecture utilises a recursive DCT algorithm to reduce the computational complexity of the distributed arithmetic algorithm in conjunction with a unique kernel framework to unify the adder matrix in accordance with the coefficient requirements. The 1D multiple integer VC-1 transform proposed in [2] uses matrix decomposition, additions, and row/column permutations as well as hardware sharing to reduce costs and also utilising in 2D transform. The resulting hardware costs of 1D and 2D transform designs are lower than those of individual designs without sharing. The methods outlined in [3] for IDCT provide efficient sharing and saving based on factor share (FS) and adder share (AS) strategies.
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