Low‐cost multi‐standard video transform core using time‐distribution scheme

Abstract

Cost-effective two-dimensional (2D) discrete cosine transform (DCT) and inverse DCT architectures capable of supporting multiple standards of MPEG, H.264 and VC-1 are presented. The proposed core utilises a 1D core and a transposed memory to achieve a low cost design. Multi-level factor share is implemented in conjunction with distributed arithmetic in a system to enable the sharing of the coefficient matrix circuit in order to reduce hardware costs. The proposed approach employs a time-distribution scheme to enable the simultaneous processing of the first and second dimensions to enhance throughput. A high efficiency of this approach was verified by fabricating a test chip using the TSMC 0.18 μm CMOS process. The architecture has an operating frequency of 200 MHz, and throughput of 800 M-pixels/s with a gate count of 44.5 K.Introduction: Video compression is widely used in applications such as video conferences, mobile video, and digital television. A variety of transform dimensions and coefficients have been developed by the International Organization for Standardization (ISO), the International Telecommunication Union Telecommunication Standardization Sector (ITU-T), and Microsoft Corporation.Discrete cosine transform (DCT) and its inverse DCT (IDCT) are the transforms most widely used in image and video compression applications due to good energy compaction. The most important issues related to DCT and IDCT transform cores are area efficiency and data throughput, and numerous novel DCT/IDCT architectures have been introduced to deal with these issues [1][2][3][4][5]. The high-speed 2D transform architecture with unique kernel for multi-standard video applications was proposed in [1]. That architecture utilises a recursive DCT algorithm to reduce the computational complexity of the distributed arithmetic algorithm in conjunction with a unique kernel framework to unify the adder matrix in accordance with the coefficient requirements. The 1D multiple integer VC-1 transform proposed in [2] uses matrix decomposition, additions, and row/column permutations as well as hardware sharing to reduce costs and also utilising in 2D transform. The resulting hardware costs of 1D and 2D transform designs are lower than those of individual designs without sharing. The methods outlined in [3] for IDCT provide efficient sharing and saving based on factor share (FS) and adder share (AS) strategies.