Low‐cost multi‐standard simultaneous forward and inverse video transform core

Abstract

This paper presents a cost-effective, two-dimensional (2-D) discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) capable of MPEG1/2/4, H.264 4 × 4/8 × 8, and VC-1 4 × 4/8 × 8/4 × 8/8 × 4 standards. We developed multilevel factor sharing in conjunction with distributed arithmetic in a scheme referred to as common sharing distributed arithmetic to enable sharing of the coefficient matrix circuit and replace multipliers with adders and shifters. By taking advantage of the similarities between DCT and IDCT transforms, we were able to implement an interlaced sorting method in a single circuit of the DCT and IDCT transform core in order to reduce area overhead while enabling the simultaneous operation of DCT and IDCT. The proposed design arranges the data of the first dimension and second dimension in order to reuse the same 1-D core to compute 2-D data. In this manner, first dimension and second dimension data of DCT and IDCT can be processed simultaneously in a single transform core. The efficacy of the proposed approach has been verified by fabricating a test chip using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm complementary metal-oxide semiconductor process. The inverse transform core was shown to have an operating frequency of 227 MHz and throughput of 454 Mpel/s with a gate count of 32.5 k. Figure 4. Time scheduling of proposed SORT1 circuit for N = 8. 1st-D, first-dimensional; 2nd-D, seconddimensional; DCT, discrete cosine transform; IDCT, inverse discrete cosine transform. 1582 Y.-H. TSENG ET AL.

High‐throughput IDCT architecture for high‐efficiency video coding (HEVC)

“…The architecture still consumes large circuit area. Several works present low-cost transpose architecture to deal with the area overhead [14][15][16][17][18]. The multiplexer is used to control the 1-D inverse discrete cosine transform (IDCT) core for the calculation of 1-D and 2-D operations, and the 1-D IDCT core uses matrix decomposition to reduce the required circuit area.…”

“…Besides, the transform size can be up to 32 × 32 in HEVC standard; thus, the transpose memory consumes large of circuit area. Several works present low-cost transpose architecture to deal with the area overhead [14][15][16][17][18].…”