A method for estimating near-interface oxide trap density in silicon carbide metal-oxide-semiconductor (MOS) capacitors by transient capacitance measurements was investigated. The fitting of the transient capacitance characteristics measured at room and low temperatures to a simple model describing the de-trapping process enables us to characterize the responses of the traps at various distances from the interface. The distribution of the trap locations in the oxide and that of response times were taken into account in this fitting. This method was applied to MOS-capacitor samples to show the significant reduction in interface state density by tuning the thermal oxidation conditions. It was found that the density of the oxide traps, especially in the spatially shallow region within several angstroms from the interface, is sensitive to thermal oxide growth conditions.
We fabricated SiO2/4H-SiC (0001) MOS capacitors with nearly-ideal capacitance-voltage characteristics, simply by the control of thermal oxidation conditions which were selected based on thermodynamic and kinetic considerations of SiC oxidation. The interface with low interface defect state density <1011 cm-2eV-1 for the energy range 0.1 – 0.4 eV below the conduction band of SiC was obtained by thermal oxidation at 1300oC in a ramp-heating furnace with a short rise/fall time, followed by low temperature O2 anneal at 800oC.
A method to characterize near-interface oxide trap density in SiC MOS capacitors using transient capacitance measurements was investigated, taking account of the distribution of de-trapping time of traps of various locations in oxide. The measurements at room and low temperatures enables us evaluate the responses of the raps of spatially deep and shallow locations, respectively. We found that the sample with low Dit
showed smaller density of near-interface traps especially in spatially shallow region in the oxide.
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