In this paper, a high-speed low-power SAR ADC is designed. In this prototype, an improved switching scheme combined with the optimized attenuation capacitor architecture is proposed, showing more power efficiency and is more suitable for high-speed data converters. Meanwhile, an improved synchronous timing strategy is employed, achieving flexible time allocation of DAC settling and comparison in each bit-cycle. In addition, a two-stage non-tail-current-source and single-phaseclock comparator is proposed with more power-efficiency and compatible resolving time. The prototype ADC is fabricated in a 40nm CMOS technology and occupies an active area of 0.04mm 2 . An SNDR of 57.18dB and an SFDR of 75.29dB are achieved with the Nyquist rate input at a sampling rate of 160MS/s, consuming 1.3mW at 1.1V supply voltage.
Capacitor mismatch problem due to process variation causes weight error, which deteriorates the linearity of SAR ADC. In this paper, a novel calibration scheme based on genetic algorithm(GA) combined with a radix-less-than-2 SAR ADC is proposed to extract the weight error caused by capacitor mismatch. This is a foreground calibration scheme and no extra injections are added. The proposed GA-based calibration scheme is simulated based on 40 nm CMOS technology. After calibration, ENOB increases from 10.19 bits to 11.46 bits, INL changes from +2.22/−2.12 LSB to +0.81/−0.80 LSB, and DNL changes from +1.79/−1.00 LSB to +0.99/−1.00LSB. As can be seen from the simulation results, the proposed calibration scheme can effectively improve the linearity deterioration caused by capacitor mismatch.
A high-speed and low-power input/output buffer for time interleaving circuit is proposed in this letter. The buffer can be applied to high-speed circuits operating at 20 GS/s. This novel two-stage buffer is employed with bandwidth expansion and slew-rate enhanced techniques. An improved common-mode feedback circuit stabilizes the output commonmode voltage. This prototype buffer is fabricated in the 45-nm COMS process, and achieves 7.2 bit ENOB at 10-GHz input frequency with power consumption of 20.4 mW, load of 0.3 fF.
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