A 10‐GHz bandwidth 45.5‐dB SNDR buffer with local feedback in 45‐nm CMOS

Abstract

A high-speed and low-power input/output buffer for time interleaving circuit is proposed in this letter. The buffer can be applied to high-speed circuits operating at 20 GS/s. This novel two-stage buffer is employed with bandwidth expansion and slew-rate enhanced techniques. An improved common-mode feedback circuit stabilizes the output commonmode voltage. This prototype buffer is fabricated in the 45-nm COMS process, and achieves 7.2 bit ENOB at 10-GHz input frequency with power consumption of 20.4 mW, load of 0.3 fF.

Guest Editorial: Digital‐based and digital‐intensive analog integrated circuits and systems

“…In such converters the input buffer is very critical and can be easily a bottleneck in terms of power and performance. This important aspect is tackled in the paper "A 10GHz bandwidth 45.5dB SNDR buffer with local feedback in 45 nm CMOS" by Jie Wu et al [12], which proposes a high-speed buffer with bandwidth expansion and slew-rate enhancement, targeting the requirements of time interleaved data converters operating at 20 GS/s. The new buffer is fabricated in 45 nm COMS process, and achieves 7.2 bit ENOB at 10GHz input frequency with consuming 20.4 mW.…”