Due to extraordinary electrical properties, preseparated, high purity semiconducting carbon nanotubes hold great potential for thin-film transistors (TFTs) and integrated circuit applications. One of the main challenges it still faces is the fabrication of air-stable n-type nanotube TFTs with industry-compatible techniques. Here in this paper, we report a novel and highly reliable method of converting the as-made p-type TFTs using preseparated semiconducting nanotubes into air-stable n-type transistors by adding a high-κ oxide passivation layer using atomic layer deposition (ALD). The n-type devices exhibit symmetric electrical performance compared with the p-type devices in terms of on-current, on/off ratio, and device mobility. Various factors affecting the conversion process, including ALD temperature, metal contact material, and channel length, have also been systematically studied by a series of designed experiments. A complementary metal-oxide-semiconductor (CMOS) inverter with rail-to-rail output, symmetric input/output behavior, and large noise margin has been further demonstrated. The excellent performance gives us the feasibility of cascading multiple stages of logic blocks and larger scale integration. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.

The development of guided chemical vapor deposition (CVD) growth of single-walled carbon nanotubes provides a great platform for wafer-scale integration of aligned nanotubes into circuits and functional electronic systems. However, the coexistence of metallic and semiconducting nanotubes is still a major obstacle for the development of carbon-nanotube-based nanoelectronics. To address this problem, we have developed a method to obtain predominantly semiconducting nanotubes from direct CVD growth. By using isopropyl alcohol (IPA) as the carbon feedstock, a semiconducting nanotube purity of above 90% is achieved, which is unambiguously confirmed by both electrical and micro-Raman measurements. Mass spectrometric study was performed to elucidate the underlying chemical mechanism. Furthermore, high performance thin-film transistors with an on/off ratio above 10(4) and mobility up to 116 cm(2)/(V·s) have been achieved using the IPA-synthesized nanotube networks grown on silicon substrate. The method reported in this contribution is easy to operate and the results are highly reproducible. Therefore, such semiconducting predominated single-walled carbon nanotubes could serve as an important building block for future practical and scalable carbon nanotube electronics.

Carbon nanotubes have the potential to spur future development in electronics due to their unequalled electrical properties. In this article, we present a review on carbon nanotube-based circuits in terms of their electrical performance in two major directions: nanoelectronics and macroelectronics. In the nanoelectronics direction, we direct our discussion to the performance of aligned carbon nanotubes for digital circuits and circuits designed for radio-frequency applications. In the macroelectronics direction, we focus our attention on the performance of thin films of carbon nanotube random networks in digital circuits, display applications, and printed electronics. In the last part, we discuss the existing challenges and future directions of nanotube-based nano-and microelectronics.

For nanotube-based electronics to become a viable alternative to silicon technology, high-density aligned carbon nanotubes are essential. In this paper, we report the combined use of low-pressure chemical vapor deposition and stacked multiple transfer to achieve high-density aligned nanotubes. By using an optimized nanotube synthesis recipe, we have achieved high-density aligned carbon nanotubes with density as high as 30 tubes/μm. In addition, a facile stacked multiple transfer technique has been developed to further increase the nanotube density to 55 tubes/μm. Furthermore, high-performance submicron carbon nanotube field-effect transistors have been fabricated on the high-density aligned nanotubes. Before removing the metallic nanotubes by electrical breakdown, the devices exhibit on-current density of 92.4 μA/μm and normalized transconductance of 13.3 μS/μm. Moreover, benchmarking with the aligned carbon nanotube transistors in the literature indicates that our devices exhibit the best performance so far, which is attributed to both the increased nanotube density and scaling down of channel length. This study shows the great potential of using such high-density aligned nanotubes for high performance nanoelectronics and analog/RF applications.

Exceptional electronic properties of graphene make it a promising candidate as a material for next generation electronics; however, self-aligned fabrication of graphene transistors has not been fully explored. In this paper, we present a scalable method for fabrication of self-aligned graphene transistors by defining a T-shaped gate on top of graphene, followed by self-aligned source and drain formation by depositing Pd with the T-gate as a shadow mask. This transistor design provides significant advantages such as elimination of misalignment, reduction of access resistance by minimizing ungated graphene, and reduced gate charging resistance. To achieve high-yield scalable fabrication, we have combined the use of large-area graphene synthesis by chemical vapor deposition, wafer-scale transfer, and e-beam lithography to deposit T-shaped top gates. The fabricated transistors with channel lengths in the range of 110-170 nm exhibited excellent performance with peak current density of 1.3 mA/μm and peak transconductance of 0.5 mS/μm, which is one of the highest transconductance values reported. In addition, the T-gate design enabled us to achieve graphene transistors with extrinsic current-gain cutoff frequency of 23 GHz and maximum oscillation frequency of 10 GHz. These results represent important steps toward self-aligned design of graphene transistors for various applications.