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This paper presents a full-CMOS Wireless Power Receiving Unit (WPRU) with high efficiency 6.78 MHz Active Rectifier and DC-DC Converter for magnetic resonant A4WP applications. The proposed high efficiency Active Rectifier with Delay Locked Loop (DLL) is a highly efficient receiver circuit intended for use in resonant wireless charging applications with a resonant frequency of 6.78 MHz. Each MOSFET of the proposed rectifier is turned on and off based on the AC input voltage.The delay between the AC input current and the AC input voltage due to the delays of internal blocks such as Voltage Limiter, Level Shifter, Gate Driver, and Comparator, will cause the reverse leakage current degrading the power efficiency. Thus, the proposed Active Rectifier adopts the Delay Locked Loop (DLL) to compensate for the delay caused by internal blocks, which leads to the removal of reverse leakage current and the power efficiency maximization. Moreover, to maximize power efficiency, Negative Impedance Circuit (Temperature (PVT) Variation to solve the efficiency reduction problem, especially by heat.This chip is implemented using 0.18 μm BCD technology with an active area of 3.5 mm x 3.5 mm.When the magnitude of the AC input voltage was 8.95 V, the maximum efficiencies of the proposed Active Rectifier and DC-DC Converter were 91.5 % and 92.7 %, respectively. The range of AC input voltage was 3 V -20 V, the efficiency of the Wireless Power Receiving Unit (WPRU) is about 80.86 %.

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This paper presents a reconfigurable radio frequency to direct current (RF-DC) converter operating at 902 MHz frequency designed to efficiently harvest RF signals and convert into useable DC voltages for RF energy harvesting applications. The proposed scheme employs a dual-path, a series (lowpower) path and a parallel (high-power) path, to maintain high power conversion efficiency (PCE) over wide input power range. The dual-path is composed of two identical rectifier blocks utilizing internal threshold voltage cancellation (IVC) technique to efficiently compensate the threshold voltage of the transistors used as rectifying devices. An adaptive control circuit (ACC) consisting of a comparator, an inverter and three switches is used in the proposed scheme. The ACC activates the series path or the parallel path to maximize the harvested power based on the input power range. The proposed scheme is designed and fabricated in a 180 nm complementary metal-oxide semiconductor (CMOS) technology. The measurement results show that PCE of the proposed circuit is above 20% from −18 dBm to −5 dBm, maintaining 13-dB input power range with peak PCE of 33% at −8 dBm for 200 k load resistance. The proposed circuit demonstrates −20.2 dBm sensitivity across 1 M load resistance while producing 1 V output DC voltage. INDEX TERMS CMOS technology, dual path, power conversion efficiency, reconfigurable, RF-DC power converter, RF energy harvesting.

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