A Design of a Wireless Power Receiving Unit With a High-Efficiency 6.78-MHz Active Rectifier Using Shared DLLs for Magnetic-Resonant A4 WP Applications

Abstract

This paper presents a full-CMOS Wireless Power Receiving Unit (WPRU) with high efficiency 6.78 MHz Active Rectifier and DC-DC Converter for magnetic resonant A4WP applications. The proposed high efficiency Active Rectifier with Delay Locked Loop (DLL) is a highly efficient receiver circuit intended for use in resonant wireless charging applications with a resonant frequency of 6.78 MHz. Each MOSFET of the proposed rectifier is turned on and off based on the AC input voltage.The delay between the AC input current and the AC input voltage due to the delays of internal blocks such as Voltage Limiter, Level Shifter, Gate Driver, and Comparator, will cause the reverse leakage current degrading the power efficiency. Thus, the proposed Active Rectifier adopts the Delay Locked Loop (DLL) to compensate for the delay caused by internal blocks, which leads to the removal of reverse leakage current and the power efficiency maximization. Moreover, to maximize power efficiency, Negative Impedance Circuit (Temperature (PVT) Variation to solve the efficiency reduction problem, especially by heat.This chip is implemented using 0.18 μm BCD technology with an active area of 3.5 mm x 3.5 mm.When the magnitude of the AC input voltage was 8.95 V, the maximum efficiencies of the proposed Active Rectifier and DC-DC Converter were 91.5 % and 92.7 %, respectively. The range of AC input voltage was 3 V -20 V, the efficiency of the Wireless Power Receiving Unit (WPRU) is about 80.86 %.

A unified DLL-controlled active rectifier in 6.78 MHz resonant-coupling wireless power receivers for space-limited portable and wearable applications

“…Compared to the previously published work of the fully NMOS transistor-based active rectifier with the shared DLL controller [7], this work unifies the two shared DLLs to only one DLL as a rectifier controller. The impact of reducing the number of DLL delay circuits is quite significant to improve the power efficiency and reduce the die area for our specified space-limited portable and wearable applica- tions.…”

“…In this letter, an 80 mW to 440 mW unified delay-locked loop (DLL)-controlled active rectifier with a compact die area of 0.612 mm 2 is presented. Compared to the previously published works with two voltage-controlled delay lines (VCDLs) [6,7], the main contribution of this work is to reduce the power loss of the rectifier control circuits by reducing one VCDL with only two additional logic elements.…”

“…To address this problem, the state-of-the-art resonant WPT receivers employ the active synchronous rectifier that replaced the diodes with the MOS transistors [4,5,6,7]. However, because of the bidirectional characteristic of the MOS transistor, it is crucial to ensure accurate switching without the reverse leakage current.…”

“…Since the compensated delay is constant with the variable amplitude of the input AC voltage, if the input voltage is sufficiently low, reverse leakage current may occur. To solve the problem of the input AC voltage dependency, dynamic compensation with DLLs has been proposed [6,7]. Compared with the PMOS cross-coupled and NMOS controlled active rectifiers [5,6], a fully NMOS transistor-based active rectifier [7] has higher voltage and current efficiency due to the low resistance of NMOS transistors.…”

“…To solve the problem of the input AC voltage dependency, dynamic compensation with DLLs has been proposed [6,7]. Compared with the PMOS cross-coupled and NMOS controlled active rectifiers [5,6], a fully NMOS transistor-based active rectifier [7] has higher voltage and current efficiency due to the low resistance of NMOS transistors. In addition, the fully NMOS integration of the rectifier still has an advantage in the hardware cost of the die area, which reduces the cost.…”