A capacitive-type touch-panel-embedded IPS-LCD is realized by a novel parasitic current reduction technique (PCR). The PCR removes 90% of the current flowing through the parasitic capacitance on a capacitive sensor (ITO layer) formed on a color filter substrate. Since the IPS-LCD has the same structure as commercial products, it features no reduction in aperture ratio.
An SOG-LCD with integrated 230kb DRAM frame memory has been demonstrated. To achieve this dense integration, a memory system architecture for horizontal stripe was developed. Memory tests proved a 1MHz operation and retention time of 166ms. Fine images are displayed both in still images and moving pictures.
A system-on-glass (SOG) DRAM intended for integrated framememories of 262k-color QCIF+ displays has been developed. An integrated codec circuit reduces the number of memory cells and layout area by a factor of 2/3. By combining the SOG-DRAM, which has a data retention time of over 16.6 ms, with an embedded controller that enables simultaneous access for writing and reading, a frame-memory has been created. The operation was verified by chip measurement and demonstration.
A system-on-glass (SOG) dynamic random access memory (DRAM), which enables the implementation of frame-memory-integrated displays, has been developed. A dynamic one-transistor-one-capacitor memory cell, which has a data retention time of over 16.6 msec, and a compression/decompression (CODEC) circuit were developed to reduce the layout area and power. The CODEC enables an 18-bit/pixel color display, while reducing the memory capacity from 18 to 12 bits/pixel. A frame-memory macro was created by combining the SOG-DRAM with an embedded controller that enables independent access for writing and reading. Its operation was verified by chip measurement and demonstration as a frame-memory operation of 262k-color QCIF+ displays. The work reported in this paper was the first step to creating a Zero-Chip Display with an integrated frame memory, and it proved the concept was feasible.
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