A 510‐kb SOG‐DRAM for mobile displays with embedded frame memories

Abstract

A system-on-glass (SOG) dynamic random access memory (DRAM), which enables the implementation of frame-memory-integrated displays, has been developed. A dynamic one-transistor-one-capacitor memory cell, which has a data retention time of over 16.6 msec, and a compression/decompression (CODEC) circuit were developed to reduce the layout area and power. The CODEC enables an 18-bit/pixel color display, while reducing the memory capacity from 18 to 12 bits/pixel. A frame-memory macro was created by combining the SOG-DRAM with an embedded controller that enables independent access for writing and reading. Its operation was verified by chip measurement and demonstration as a frame-memory operation of 262k-color QCIF+ displays. The work reported in this paper was the first step to creating a Zero-Chip Display with an integrated frame memory, and it proved the concept was feasible.