This paper presents a 10-bit single-ended SAR ADC suitable for multi-channel neural recording. The proposed ADC introduces several power saving techniques to boost the energy efficiency. The ADC is built with on-chip common-mode buffer for input tracking, which is reused as the pre-amplifier of a current-mode comparator during conversion. A small capacitor is inserted between the amplifier and the capacitive DAC array in order to reduce the capacitive load on the amplifier. A split capacitor array with dual thermometer decoders is proposed to reduce the switching energy. Implemented in 0.13-CMOS technology, the ADC achieved a maximum differential nonlinearity (DNL) of 0.33/ 0.56 LSB, maximum integral nonlinearity (INL) of 0.61/ 0.55 LSB, effective number-of-bits (ENOB) of 8.8, and a power consumption of 9-.Index Terms-ADC, analog-to-digital converter, low power, low voltage, multi-channel, SAR, successive approximation.
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Owing to the conductivity modulation of silicon carbide (SiC) bipolar devices, n-channel insulated gate bipolar transistors (n-IGBTs) have a significant advantage over metal oxide semiconductor field effect transistors (MOSFETs) in ultra high voltage (UHV) applications. In this paper, backside grinding and laser annealing process were carried out to fabricate 4H-SiC n-IGBTs. The thickness of a drift layer was 120 μm, which was designed for a blocking voltage of 13 kV. The n-IGBTs carried a collector current density of 24 A/cm2 at a power dissipation of 300 W/cm2 when the gate voltage was 20 V, with a differential specific on-resistance of 140 mΩ·cm2.
A 4H-SiC MOSFET with breakdown voltage higher than 3300 V has been successfully designed and fabricated. Numerical simulations have been performed to optimize the parameters of the drift layer and DMOSFET cell structure of active area. The n-type epilayer is 33 μm thick with a doping of 2.5 × 1015 cm−3. The devices were fabricated with a floating guard ring edge termination. The drain current Id = 5 A at Vg = 20 V, corresponding to Vd = 2.5 V.
This paper presents a 15-channel, 30-V, implantable current stimulator for restoring locomotion control after spinal cord injuries. The stimulator features performance specifications comparable to those of large desktop instrumentation: high linearity, high precision of the delivered currents, small channel-to-channel mismatches and a fast settling time of 0.3 μs. An ADC-based active charge balancing scheme using a digital PI (proportional–integral) controller was implemented in firmware.
The design, fabrication, and electrical characteristics of the 4H-SiC JBS diode with a breakdown voltage higher than 10 kV are presented. 60 floating guard rings have been used in the fabrication. Numerical simulations have been performed to select the doping level and thickness of the drift layer and the effectiveness of the edge termination technique. The n-type epilayer is 100 μm in thickness with a doping of 6 × 1014 cm−3. The on-state voltage was 2.7 V at JF = 13 A/cm2.
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