A 0.8-V, 1-MS/s, 10-bit SAR ADC for Multi-Channel Neural Recording

Tao, Yonghong; Lian, Yong

doi:10.1109/tcsi.2014.2360762

Cited by 37 publications

(14 citation statements)

References 38 publications

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“…These two shortcomings make the conventional flash ADC unsuitable for SoC systems. Several recent designs that have smaller area have been reported such as those in other studies 6–36 …”

Section: Problem Statement and Previous Workmentioning

confidence: 99%

A novel flash‐like all‐metal‐oxide semiconductor analog‐to‐digital converter suitable for system on chips systems

Abdalla

2020

Circuit Theory & Apps

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Summary The analog‐to‐digital converters (ADCs) play a very important role in electronic products, radar, communication systems and signal processing, to name such a few. In this paper, a novel all‐metal‐oxide semiconductor (MOS) flash‐like analog‐to‐digital converter (FLADC) that consists of five stages is proposed. The design was performed using only MOS transistors, and the proposed ADC works in a way similar to the conventional flash ADC. According to the proposed ADC, there is no need for the comparators used in the conventional flash ADCs, thus resulting in a reduction in both the transistor count and the power consumption. The sound operation and the superiority of the proposed ADC compared to previous works is verified by simulation using the 0.13‐μm complementary MOS (CMOS) technology with a power‐supply voltage, VDD, of 1.2 V. The simulation has been conducted on a 5‐bit FLADC that is built by 276 MOS transistors only which is approximately 32% of the transistor count of the corresponding conventional flash ADC and has no resistors. According to the simulation results, the proposed 5‐bit FLADC consumes 3.23 mW at sampling rate of 0.5 GS/s.

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“…These two shortcomings make the conventional flash ADC unsuitable for SoC systems. Several recent designs that have smaller area have been reported such as those in other studies 6–36 …”

Section: Problem Statement and Previous Workmentioning

confidence: 99%

A novel flash‐like all‐metal‐oxide semiconductor analog‐to‐digital converter suitable for system on chips systems

Abdalla

2020

Circuit Theory & Apps

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“…Generally such a configuration will favour high density vertical metal-insulatormetal (MIM) capacitors that have large minimum size requirements and can be placed over active circuitry to reduce silicon footprint. In fact by using a split capacitor configuration the size of C U can be even larger with less elements in the array for the same sampling capacitance leading to very efficient utilization of MIM capacitor area [21]. It may still be the case that C U is smaller than the minimum capacitance C min for intermediate precision of 6-10 bits.…”

Section: A Topology Optimizationmentioning

confidence: 99%

A 0.016 mm2 12 b $\Delta \Sigma $ SAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays

Leene

Constandinou

2017

IEEE Trans. Circuits Syst. I

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The instrumentation systems for implantable brainmachine interfaces represent one of the most demanding applications for ultra low-power analogue-to-digital-converters (ADC) to date. To address this challenge, this paper proposes a SAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0-2 MASH topology. This configuration uses a specialized FIR window to decimate the modulator output and reject mismatch errors from the SAR quantizer, which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision. A fully differential prototype was fabricated using 0.18 μm CMOS to demonstrate 10.8 ENOB precision with a 0.016 mm 2 silicon footprint. Moreover, a 14 fJ/conv figure-of-merit can be achieved, while resolving signals with the maximum input amplitude of ±1.2 Vpp sampled at 200 kS/s. The ADC topology exhibits a number of promising characteristics for both high speed and ultra low-power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio, which are critical parameters for many sensor applications. Index Terms-A/D conversion, bio-sensors arrays, oversampling, incremental delta-sigma, FIR decimation, low power analogue, ADC calibration. I. INTRODUCTION T HE emergent market for wearable electronics and implantable devices for personalized health care has resulted in a growing demand for miniaturized battery powered systems that wirelessly connect a network of sensors [1]. These systems rely extensively on high precision analogue to digital conversion to leverage digital processing techniques and accommodate stringent diagnostic requirements [2]. As a result the ADC power, area, and precision can have a profound impact on a system's overall capabilities. For this reason oversampling techniques using ADCs have already been used extensively to accommodate the niche characteristics of biomedical devices and acquire low frequency bio-signals [3]. More recent developments allow these techniques to be more applicable to large sensor arrays using an incremental analogue to digital converter (IADC) topology [4]. This is in contrast to the conventional use where a single oversampling ADC continuously converts the signal from a single sensing unit with exceptional efficiency. IADC designs are unique in Manuscript

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“…In order to achieve such capacitance density, smaller parasitic capacitance and higher speed, in [7,8,9,10,11,12], MOM capacitance is used as a weighted capacitor array. In order to reduce the error introduced by weight capacitor mismatch, more and more SAR ADCs use non-binary capacitor arrays to provide redundancy for correction errors [4,7,8,9,10,13,14]. In order to reduce the overall capacitance value and the total number of capacitors per unit, the split capacitor array becomes a capacitor array commonly used by many SAR ADCs [5,6,13,15,16], which connects different groups of capacitors with series capacitors.…”

Section: Introductionmentioning

confidence: 99%

“…In order to reduce the error introduced by weight capacitor mismatch, more and more SAR ADCs use non-binary capacitor arrays to provide redundancy for correction errors [4,7,8,9,10,13,14]. In order to reduce the overall capacitance value and the total number of capacitors per unit, the split capacitor array becomes a capacitor array commonly used by many SAR ADCs [5,6,13,15,16], which connects different groups of capacitors with series capacitors. However, from the existing literature, non-binary split array ADC using MOM capacitor has not been reported.…”

Section: Introductionmentioning

confidence: 99%

A lateral field non-binary split weighted capacitor array based on fractal curve for SAR ADC

Zhao

Zhang

Wenxin

2020

IEICE Electron. Express

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A non-binary split-type MOM weighted capacitor array based on fractal geometry for SAR (Successive Approximation Register) ADC is proposed. By taking advantage of the geometric characteristics of the Hilbert curve, the capacitor array avoids the use of complex commoncentroid structure and complex wiring. The test results of the SAR ADC using this capacitor array show that, the measured DNL and INL were −0.26/0.38 LSBs and −0.37/0.38 LSBs, respectively. The ENOB is 8.66 bits. The SAR ADC was implemented using a 180-nm CMOS process with a supply voltage of 1.8 V. Its active area and power consumption are 330 µm × 1190 µm and 1.89 mW, respectively.

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A 0.8-V, 1-MS/s, 10-bit SAR ADC for Multi-Channel Neural Recording

Cited by 37 publications

References 38 publications

A novel flash‐like all‐metal‐oxide semiconductor analog‐to‐digital converter suitable for system on chips systems

A novel flash‐like all‐metal‐oxide semiconductor analog‐to‐digital converter suitable for system on chips systems

A 0.016 mm2 12 b $\Delta \Sigma $ SAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays

A lateral field non-binary split weighted capacitor array based on fractal curve for SAR ADC

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