Design and fabrication of a 3.3 kV 4H-SiC MOSFET

Abstract

A 4H-SiC MOSFET with breakdown voltage higher than 3300 V has been successfully designed and fabricated. Numerical simulations have been performed to optimize the parameters of the drift layer and DMOSFET cell structure of active area. The n-type epilayer is 33 μm thick with a doping of 2.5 × 1015 cm−3. The devices were fabricated with a floating guard ring edge termination. The drain current Id = 5 A at Vg = 20 V, corresponding to Vd = 2.5 V.

3C-SiC Transistor With Ohmic Contacts Defined at Room Temperature

“…Alloyed Ni is commonly used for both in 4H-SiC power devices [37,38], similarity we believe the as-deposited Ti/Ni bilayer proposed here can also be integrated. The low thermal budget of the process demonstrated in this work opens new doors to the application of SiC transistors with other low temperature technologies, including high k dielectrics atomic layer deposited (e.g.…”

Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique

“…To implement the SiC NMOS and PMOS while ensuring compatibility with the SiC power device processing technology, the CMOS configura-tion in Fig. 1 is adopted [7,8] . The PMOS is formed directly in the drift layer, while the NMOS is fabricated in a P-well.…”

“…Developing SiC integrated circuits (ICs) is beneficial for realizing the full potential of SiC material in high temperature applications [2−6] . Compared with other technology, the complementary-metal-oxide-semiconductor (CMOS) technology could achieve full railto-rail output voltage switching, low power losses and temperature-independent logic levels [7,8] . Unfortunately, the reported SiC CMOS ICs in the literature are fabricated using specially developed technology, which is not compatible with the mainstream 4H-SiC power device processing technology.…”

Different JFET Designs on Conduction and Short-Circuit Capability for 3.3 kV Planar-Gate Silicon Carbide MOSFETs

“…The JD region is formed by multiple high-energy N implantation, and the implant depth is 0.8 µm from surface with doping concentration of 1×10 17 cm - In order to further investigate physics of the fabricated SiC MOSFETs, a detailed MOSFET structure is constructed accordingly through Sentaurus TCAD software. For static characteristics, the following models are used, including Shockley-Read-Hall and Auger recombination model, avalanche generation, band-gap narrowing, impact ionization, incomplete ionization model, and traps and fixed charges model [12]. For SC characteristics, the thermodynamic model, full anisotropy and temperature dependence of thermal material properties are added.…”