Stretchable electronics represents a relatively recent class of technology [1,2] of interest partly due to its potential for applications in sensory robotic skins, [3,4] conformal photovoltaic modules, [5,6] wearable communication devices, [7,8] skin-mounted monitors of physiological health, [9][10][11] advanced, soft surgical and clinical diagnostic tools, [11,12] and bioinspired digital cameras. [13,14] A key challenge in each of these systems is in the development of strategies in mechanics that simultaneously allow large levels of elastic stretchability and high areal coverages of active devices built with materials that are themselves not stretchable (e.g., conventional metals) and are, in some cases, highly brittle (e.g., inorganic semiconductors). For design approaches that embed stretchability in interconnect structures that join rigid device islands, the system level stretchability ε system is much smaller than the interconnect stretchability ε interconnect . Zhang et al. [15] identified the following relationship between the interconnect and system stretchability:, where f dev = (area of active device components)/(total area of the system) is the areal coverage ratio of active device components. Structure designs for stretchable interconnects have evolved from straight [13,16] to curvilinear interconnects, [17] from those bonded to or embedded in the supporting substrate [11,18] to free-standing designs housed in microfluidic enclosures, [19] and from simple structures [17] to fractal/self-similar designs. [15,[20][21][22] All such cases, including a broad variety of shapes, sizes, and geometric arrangements, share the same underlying mechanisms, i.e., out-of-plane buckling of thin structures (metals, insulators, or semiconductors with thickness typically between ≈100 nm and ≈1 µm) provides the basis for elastic stretchability. The most advanced interconnects achieve elastic (reversible)

The use of fractal-inspired geometric designs in electrical interconnects represents an important approach to simultaneously achieve large stretchability and high aerial coverage of active devices for stretchable electronics. The elastic stiffness of fractal interconnects is determined analytically in this paper. Specifically, the elastic energy and the tensile stiffness for an order n fractal interconnect of arbitrary shape are obtained, and are verified by the finite element analysis and experiments.

Abstract. We propose a reflectance fiber bundle microscope using a dark-field illumination configuration for applications in endoscopic medical imaging and diagnostics. Our experiment results show that dark-field illumination can effectively suppress strong specular reflection from the proximal end of the fiber bundle. We realized a lateral resolution of 4.4 μm using the dark-field illuminated fiber bundle configuration. To demonstrate the feasibility of using the system to study cell morphology, we obtained still and video images of two thyroid cancer cell lines. Our results clearly allow differentiation of different cancer cell types. C 2011 Society of Photo-Optical Instrumentation Engineers (SPIE).

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The interfacial and electrical properties of Ge-based metal-oxide-semiconductor (MOS) capacitor with high-k gate dielectric of HfTiO and passivation interlayer of LaTaON are investigated. Experimental results show the Ge MOS with HfTiO/LaTaON gate-stacked dielectric exhibits low interfacestate density (7.8 × 10 11 cm −2 eV −1 ), small gate-leakage current (7.88 × 10 −4 A cm −2 at V g − V fb = 1 V), small capacitance equivalent thickness (1.1 nm), and large equivalent dielectric constant (27.7). X-ray photoelectron spectroscopy and transmission electron microscopy reveal that the improvements should be due to the fact that La/Ta-based oxide/oxynitride has excellent interface properties with Ge, and the LaTaON interlayer can effectively block the in-diffusion of oxygen and the out-diffusion of germanium, thus suppressing the growth of low-k GeO x and intermixing between Ge and Hf.Index Terms-Ge metal-oxide-semiconductor (Ge MOS), high-k dielectric, interface properties, LaTaON, passivation layer.

Flip chip packaging as a mainstream packaging interconnect technology has proliferated rapidly within the last decade or so. With the applications of high-performance chip, its thickness and size have been much thinner and bigger, which is challenging the current assembly technique, especially for the reliable peeling of ultrathin die from the wafer due to its vulnerability and flexibility. Here, we present some significant analytical formulas to estimate die cracking stress and peeling energy in die peeling process. The effects of two factors, including peeling cracking propagation and ejecting needle configuration, are investigated using a fracture mechanics framework. Meanwhile, all analytical predictions have been verified via finite element modeling with virtual crack technique. Theoretical results have shown that die cracking stress could be effectively reduced, but it rarely works to improve peeling energy when more needles are embedded below the adhesive tape. In particular, the essence of the technique with the multineedle is discussed, compared with the normal single-needle technique, which can be used to guide the design of ultrathin die peeling process.Index Terms-Adhesive layer, chip peeling-off, die-cracking stress, energy release rate (ERR), microelectronic packaging, multineedle ejector.

In this paper, the behavior of ejected jet is studied at three different substrates (conductive, semiconductor and dielectric) in continuous electrohydrodynamic inkjet printing mode. Because the polarization charges will accumulate at the surface of the substrate in a short nozzle-to-collector distance, one can observe that the different flight behavior in the space. Results show that the substrate has little effect on the threshold voltage and the relaxation time of the substrate can be used to indicate the behavior of the jet. When the lifetime of the jet is larger than the relaxation time of the substrate, the jet can be deposited on the substrate regularly. Based on this guideline, a designed parallel lines and grid pattern are fabricated with several micrometers on a silicon substrate. These show that the designed pattern could be fabricated in a controllable jet. In the future, this method is able to be utilized to fabricate the mirco/nano-devices.

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