The channel temperature (Tch) and thermal resistance (Rth) of Ga2O3 metal-oxide-semiconductor field-effect transistors were investigated through electrical measurements complemented by electrothermal device simulations that incorporated experimental Ga2O3 thermal parameters. The analysis technique was based on a comparison between DC and pulsed drain currents (IDS) at known applied biases, where negligible self-heating under pulsed conditions enabled approximation of Tch to the ambient temperature (Tamb) and hence correlation of IDS to Tch. Validation of the device model was achieved through calibration against the DC data. The experimental Tch was in good agreement with simulations for Tamb between 20 °C and 175 °C. A large Rth of 48 mm·K/W thus extracted at room temperature highlights the value of thermal analysis for understanding the degradation mechanisms and improving the reliability of Ga2O3 power devices.
A vertical β-Ga2O3 metal–oxide–semiconductor field-effect transistor featuring a planar-gate architecture is presented. The device was fabricated by an all-ion-implanted process without requiring trench etching or epitaxial regrowth. A Mg-ion-implanted current blocking layer (CBL) provided electrical isolation between the source and the drain except at an aperture opening through which drain current was conducted. Successful transistor action was realized by gating a Si-ion-implanted channel above the CBL. Thermal diffusion of Mg induced a large source–drain leakage current through the CBL, which resulted in compromised off-state device characteristics as well as a reduced peak extrinsic transconductance compared with the results of simulations.
The dynamic characteristics of a 4H-SiC insulated-gate bipolar transistor (IGBT) at pulse switching is investigated by incorporating reported measurements of the interface defect density to device simulation. Different trap features such as energy states and trap time constants are investigated to determine the influence of traps on circuit performance. The capture cross-section parameter used in the simulation depicts the probability of traps to trap/detrap carriers which relates to the carrier trap time constant. It is demonstrated that trapped carriers from the on-state condition cause enhanced generation current during the off-state condition, which give rise to undesired leakage current in addition to the threshold voltage shift previously reported. The device power dissipation is increased by a factor of 100 due to the defects.
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