Investigation of 4H-SiC insulated-gate bipolar transistor turn-off performance for achieving low power loss

Abstract

The dynamic characteristics of a 4H-SiC insulated-gate bipolar transistor (IGBT) at pulse switching is investigated by incorporating reported measurements of the interface defect density to device simulation. Different trap features such as energy states and trap time constants are investigated to determine the influence of traps on circuit performance. The capture cross-section parameter used in the simulation depicts the probability of traps to trap/detrap carriers which relates to the carrier trap time constant. It is demonstrated that trapped carriers from the on-state condition cause enhanced generation current during the off-state condition, which give rise to undesired leakage current in addition to the threshold voltage shift previously reported. The device power dissipation is increased by a factor of 100 due to the defects.

Investigation of analytical model of turn-off loss for 4H-SiC high-voltage trench insulated gate bipolar transistors

“…However, over the past decades, the majority of studies have focused on how to improve device electrical characteristics, and only a few studies have reported on the analytical models and theoretical analyses of the transient turn-off in 4H-SiC IGBTs. [15][16][17][18][19][20][21] In this paper, a mathematical analytical model of the turn-off in n-channel 15 kV trench-gate 4H-SiC IGBTs based on the hole-carrier concentration profile in N-drift region is developed and verified by a numerical simulation using a two-dimensional ATLAS simulator. 22) Moreover, the effect of the carrier lifetime in the N-drift region on turn-off loss has also been investigated.…”

Enhanced Miller plateau characteristics of a 4H-SiC insulated-gate bipolar transistor in the presence of interface traps

“…[4][5][6] In the presence of traps, the SiC IGBT static characteristics suffers from threshold voltage instability and high on-resistance. [7][8][9][10][11][12][13][14][15][16][17][18][19] Figure 2(b) shows that the deep trap states shift the threshold voltage to higher voltages. The shallow trap states decrease the current at higher gate voltage and on a wide range.…”