Characterization of channel temperature in Ga2O3 metal-oxide-semiconductor field-effect transistors by electrical measurements and thermal modeling

Abstract

The channel temperature (Tch) and thermal resistance (Rth) of Ga2O3 metal-oxide-semiconductor field-effect transistors were investigated through electrical measurements complemented by electrothermal device simulations that incorporated experimental Ga2O3 thermal parameters. The analysis technique was based on a comparison between DC and pulsed drain currents (IDS) at known applied biases, where negligible self-heating under pulsed conditions enabled approximation of Tch to the ambient temperature (Tamb) and hence correlation of IDS to Tch. Validation of the device model was achieved through calibration against the DC data. The experimental Tch was in good agreement with simulations for Tamb between 20 °C and 175 °C. A large Rth of 48 mm·K/W thus extracted at room temperature highlights the value of thermal analysis for understanding the degradation mechanisms and improving the reliability of Ga2O3 power devices.

In Situ Characterization and Modification of β‐Ga2O3 Flakes Using an Ion Micro‐Probe

“…However, for a direct comparison of IL quenching (measured without applying any bias) and electrical properties another effect needs to be taken into account and studied in more detail in the future. Considering the low thermal conductivity of β‐Ga 2 O 3 , the influence of self‐thermal‐heating on the possible damage recovery during the I–V curves cannot be discarded …”

A novel β‐Ga2O3 HEMT with fT of 166 GHz and X‐band POUT of 2.91 W/mm

“…However, under the thermal effects, at 250 C, the output current drops by approximately 50% of the value at room temperature. 35 Likewise, when contact resistance of 0.4 Ω-mm, as reported in experimental device 21 used for both ohmic contacts, I DMAX drops by approximately 35% over perfect ohmic contacts.…”

“…Recently, using thermal simulation, various studies on measurement of thermal resistance (TR) and peak lattice temperature in β-Ga 2 O 3 devices are reported. [35][36][37][38][39][40] Different substrates with high thermal conductivity including diamond, sapphire, and AlN were integrated along with thinning down β-Ga 2 O 3 substrate as bottom-side passive cooling solution. Furthermore, Tadjer et al 38 examined highly conductive Cu substrate and found 20 times improvement in output power density over β-Ga 2 O 3 substrate under targeted device temperature 175 C. However, these bottom-side cooling approaches let go of the high quality single crystal Ga 2 O 3 native substrate-one of the key motivations of Ga 2 O 3 technology.…”

High Performance ${\beta}$ -Ga2O3 Nano-Membrane Field Effect Transistors on a High Thermal Conductivity Diamond Substrate

“…And low-cost large-size β-Ga 2 O 3 native bulk substrates can be potentially realized by melt-grown methods [6]- [7]. However, the β-Ga 2 O 3 bulk substrate has a low thermal conductivity (κ) of 10-25 W/m•K and thus severe self-heating effects (SHE) can be observed [8]. In high-power electronic devices, the output power density (P) and maximum drain current (I D ) can be significantly limited by elevated channel temperature caused by SHE [9], [10] and it has become a key challenges in β-Ga 2 O 3 research because elevated temperature degrades electron mobility in β-Ga 2 O 3 [8], [11]- [13].…”

“…However, the β-Ga 2 O 3 bulk substrate has a low thermal conductivity (κ) of 10-25 W/m•K and thus severe self-heating effects (SHE) can be observed [8]. In high-power electronic devices, the output power density (P) and maximum drain current (I D ) can be significantly limited by elevated channel temperature caused by SHE [9], [10] and it has become a key challenges in β-Ga 2 O 3 research because elevated temperature degrades electron mobility in β-Ga 2 O 3 [8], [11]- [13]. In addition, high channel temperature can also severely degrade the gate dielectric, device variability, and long-term reliability [8], [14].…”