This paper presents for the first time a full 32nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (A VT ) improvement (A VT~2 .8mV.um) and low 1/f noise aligned with poly SiON are reported. Excellent Static Noise Margin (SNM) of 213mV has been achieved at low voltage for a high density 0.157um 2 SRAM cell. Hierarchical BEOL based on Extreme Low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125ºC.
In this work, we propose an efficient reconstruction scheme for compressive sensing (CS) of fiber Bragg grating (FBG) spectrum. Taking advantage of the sparse reflection spectrum of the FBG array network, we have demonstrated the use of CS for compressing the spectrum at an excessively high compression factor up to 64. In addition to that, the spectral difference (SD) of the spectra is used to further enhance their sparsity for the CS model. In this investigation, four different configurations have been devised and tested to compare their performance and effectiveness. Configuration IV that is based on SD and deep neural network offers the best recovery performance. The proposed method is a potential tool for efficient data storage and transmission for FBG sensor network.
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