We report on the fabrication and modification of a top-down nanofabrication platform for enormous parallel silicon nanowire-based devices. We explain the nanowire formation in detail, using an additive hybrid lithography step, optimising a reactive ion etching recipe for obtaining smooth and vertical nanowires under a hybrid mask, and embedding the nanowire in a dielectric membrane. The nanowires are used as a sacrificial template, removal of the nanowires forms arrays of well-defined nano-pores with a high surface density. This platform is expected to find applications in many different physical domains, including nanofluidics, (3D) nanoelectronics, as well as nanophotonics. We demonstrate the employment of the platform as field emitter arrays, as well as a state-of-the-art electro-osmotic pump.
This paper introduces a new self-aligned procedure for wafer-scale fabrication of curved metal-insulatorsemiconductor (cMIS) tunneling junctions with nanometric lateral dimensions. The fabrication process is based on the use of an array of silicon nano-pillars embedded in a silicon nitride membrane. The junctions are formed at the apex of pyramidal pits and the tunneling window is defined using self-aligned corner lithography. The current densities of the functional cMIS-junctions with a 2.5 nm thick tunneling oxide layer are in the theoretically expected range.
High-density arrays of silicon wedges bound by {111}
planes on
silicon (100) wafers have been created by combining convex corner
lithography on a silicon dioxide hard mask with anisotropic, crystallographic
etching in a repetitive, self-aligned multiplication procedure. A
mean pitch of around 30 nm has been achieved, based on an initial
pitch of ∼120 nm obtained through displacement Talbot lithography.
The typical resolution of the convex corner lithography was reduced
to the sub-10 nm range by employing an 8 nm silicon dioxide mask layer
(measured on the {111} planes). Nanogaps of 6 nm and freestanding
silicon dioxide flaps as thin as 1–2 nm can be obtained when
etching the silicon at the exposed apices of the wedges. To enable
the repetitive procedure, it was necessary to protect the concave
corners between the wedges through “concave” corner
lithography. The produced high-density arrays of wedges offer a promising
template for the fabrication of large arrays of nanodevices in various
domains with relevant details in the sub-10 nm range.
A novel wafer-scale silicon fractal fabrication method is presented here for forming pyramids only in the lateral direction using the crystal orientation of silicon. Fractals are fabricated in silicon by masking only the corners (corner lithography) of a cavity in silicon with silicon nitride, where the shape is determined by the crystal {111} planes of the silicon. The octahedral cavity shaped by the {111} planes was previously only used for forming octahedral fractals in all directions, but by using a planar silicon dioxide hard-mask on a silicon (100) wafer, the silicon octahedral cavity is “cut in half”. This creates a pyramid with sharper edges and vertices at its base than those determined by just the {111} planes. This allows selective corner lithography patterning at the vertices of the base while leaving the apex unpatterned, leading to lateral growing of pyramidal fractals. This selective patterning is shown mathematically and then demonstrated by creating a fractal of four generations, with the initial pyramid being 8 µm and the two final generations being of submicron size.
Known templating procedures mostly create out-ofplane nanowires where individual connections at both ends are complicated. Here we introduce a templating procedure for wafer scale fabrication of in-plane nanowires. The template fabrication process employs two simple interference lithography masking patterns and relies on self-aligned crystallographic processing. In-plane nanowires with diameters down to 10 nm can be fabricated wafer scale through this 3D templating procedure. As a first demonstration arrays of suspended silicon nitride wires have been created.
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