Wafer-Scale Self-Aligned Fabrication of Nanometric Curved Tunneling Junctions

Abstract

This paper introduces a new self-aligned procedure for wafer-scale fabrication of curved metal-insulatorsemiconductor (cMIS) tunneling junctions with nanometric lateral dimensions. The fabrication process is based on the use of an array of silicon nano-pillars embedded in a silicon nitride membrane. The junctions are formed at the apex of pyramidal pits and the tunneling window is defined using self-aligned corner lithography. The current densities of the functional cMIS-junctions with a 2.5 nm thick tunneling oxide layer are in the theoretically expected range.

Wafer-scale fabrication and modification of silicon nano-pillar arrays for nanoelectronics, nanofluidics and beyond

“…In this paragraph, we discuss the effects of varying the process settings and the RIE plasma conditions upon etching SiNWs. The initial process recipe was optimised for etching straight SiNWs of ~250 nm in height after 60 s of etching SiNWs under a full-wafer-scale DTL fabricated PFI+BARC mask [4]. Considering a 100 mm diameter substrate, and 250 nm wide square unit cell containing the PFI+BARC columns, the silicon loading to which the process was initially optimised was ~87%.…”

“…The effect of the smaller loading is immediately apparent; an extensive amount of barrelling is observed yielding thin SiNWs. The initial full wafer-scale recipe, [4], performs well on the full wafer-scale and is used for the etching of the SiNWs in the case of the fabrication of massively parallel EOF pump, with 50 sccm C 4 F 8 flow, but etches too fast on the hybrid mask substrate. Subsequently, the SF 6 flow was reduced with 3 sccm to reduce the etch-rate, run 1.2 in Table 2.…”

“…An example is the implementation in high areal density memory chips (3D-NAND technology), other examples of applications are e.g., vacuum electronics, display technology, or field emitters in multi-beam electron lithography [1][2][3]. In the context of energy harvesting systems, we have developed a 'curved' metal -insulatorsemiconductor (cMIS) tunnel diode based on nano-pillar technology [4].…”