A 6-bit Ku band digital step attenuator with low phase variation is presented in this paper. The attenuator is designed with 0.13-μm SiGe BiCMOS process technology using triple well isolation N-Metal-Oxide-Semiconductor (TWNMOS) and through-silicon-via (TSV). TWNMOS is mainly used to improve the performance of switches and reduce the insertion loss (IL). TSV is utilized to provide approximately ideal global current ground plane with low impedance for the attenuator. In addition, substrate floating technique and new capacitance compensation technique are adopted in the attenuator to improve the linearity and decrease the phase variation. The measured results show that the attenuator IL is 6.99–9.33 dB; the maximum relative attenuation is 31.87–30.31 dB with 0.5-dB step (64 states), the root mean square (RMS) for the amplitude error is 0.58–0.36 dB and the phase error RMS is 2.06–3.46° in the 12–17 GHz frequency range. The total chip area is 1 × 0.9 mm2.
A 6-bit digitally controlled active phase shifter is implemented in 0.13-µm SiGe BiCMOS process for 6-18 GHz phased-arrays. An input passive balun with center open stub is applied to split the single input to differential and achieve high amplitude/phase balance. A degenerated-Q quadrature all-pass filter (QAF) is used to generate two orthogonal vectors with high I/Q accuracy over a wide bandwidth and a main digital-toanalog convertor (DAC) controls the I/Q amplitude to achieve 6-bit phase resolution. In addition, a calibration DAC is adopted to compensate the amplitude variations and the phase error introduced by balun and QAF. Consequently, high resolution along with low gain/phase error can be achieved. The phase shifter has achieved root mean square (RMS) phase error of <4.36°, and RMS gain error of <1.04 dB for all 6-bit phase states at 6-18 GHz. The power gain ranges from 0.95 dB at 6 GHz to −1.85 dB at 18 GHz. Input 1 dB compression point (IP −1dB) is 5.4-8 dBm at 6-18 GHz for 0°-phase state. The total power consumption is 74.4 mW, and the overall chip size is 1.8 × 1.3 mm 2 .
This paper presents a low-voltage ZigBee transceiver covering a unique frequency band of 780/868/915/2400 MHz in 180 nm CMOS technology. The design consists of a receiver with a wideband variable-gain front end and a complex band-pass filter (CBPF) based on poles construction, a transmitter employing the two-point direct-modulation structure, a Ʃ-Δ fractional-N frequency synthesizer with two VCOs and some auxiliary circuits. The measured results show that under 1 V supply voltage, the receiver reaches −93.8 dBm and −102 dBm sensitivity for 2.4 GHz and sub-GHz band, respectively, and dissipates only 1.42 mW power. The frequency synthesizer achieves −106.8 dBc/Hz and −116.7 dBc/Hz phase noise at 1 MHz frequency offset along with 4.2 mW and 3.5 mW power consumption for 2.4 GHz and sub-GHz band, respectively. The transmitter features 2.67 dBm and 12.65 dBm maximum output power at the expense of 21.2 mW and 69.5 mW power for 2.4 GHz and sub-GHz band, respectively.
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