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The effects of Enterococcus faecium on growth, intestinal barrier function, and immune response in Escherichia coli O78-challenged broiler chickens were investigated. Three hundred eight 1-day-old Ross male chickens were randomly assigned into three treatment groups: negative control (C), E. coli O78-infected positive (EP), and E. coli O78-infected with 200 mg/kg E. faecium dietary supplementation (EF). E. faecium significantly increased the body weight on day 10 (P < 0.05) and day 15. Furthermore, these birds had a greater average daily gain compared with the other groups during days 1-10 (P < 0.05). The death rate of the EF chickens dramatically declined. E. faecium supplementation improved the jejunal villus height and the ratio of villus height to crypt depth (P < 0.05) 3 and 7 days post-infection. The mRNA expression of claudin-1 significantly increased by E. faecium (P < 0.05) 3 and 7 days post-infection, and Mucin2 was markedly enhanced (P < 0.05) 3 days post-infection. E. faecium upregulated the mRNA expression of PPAR-γ and IL-10 (P < 0.05) and downregulated that of NF-κB, TLR4, and IL-1β (P < 0.05) in the spleen 3 and 7 days post-infection. Lipopolysaccharide stimulation index was markedly enhanced in the EF group (P < 0.05) 3 days post-infection. The increased liver E. coli number caused by the E. coli O78 challenge was significantly reversed by E. faecium (P < 0.05). E. faecium improved growth and reduced the death rate by regulating the immune response and maintaining the intestinal integrity in E. coli O78-challenged broiler chickens.

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Source-series-terminated (SST) transmitters consume ¼ the output stage power of CML drivers [1], but their adoption in industry-standard multi-protocol SerDes has been stunted by difficulties in achieving flexible swings, constant current equalization, and supporting DC-coupled voltage standards drafted with CML in mind. Fundamentally, CML drivers separate the termination control from the switching devices, allowing current summing techniques to implement output level control and transmitter equalization (EQ). In this paper, the architecture and circuits of an equally flexible SST transmitter is presented that overcomes these challenges through the use of ground regulation, P-to-N shunting legs, and partially weighted segments. The clocks and datapath dissipate 32mW at 7.4Gb/s with an 800mV differential swing. Target protocols include PCIe Gen1/2, XAUI, Fibre Channel (FC) 1/2/4, CEI6 SR and SATA 1/2. Figure 20.6.1 shows the block diagram of the transmitter. The entire datapath, including the clocks, switches between Vtt and a regulated supply, Vs, adjustable between 780 and 920mV below Vtt. The reduced swing allows thin-oxide devices to be used in the output stages with a 1.0 to 1.65V Vtt. By referencing the regulated supply to Vtt, the design is compliant to protocols specifying CML voltage levels (e.g., CEI6). The regulator minimizes the amount of impedance adjustability required and supply-induced jitter. Since the entire datapath operates at this reduced level, less power is consumed and requisite level shifting is done in the parallel domain, well in advance of jitter critical stages.A 1/12 replica of the driver is used to calibrate a single slice. Separate calibration codes are generated for the pull-up (PU) and pull-down (PD) paths by comparing the series combination of the resistor (a tight tolerance across PVT reduces the required adjustability range) and transistors to an external reference. These codes are applied to the final stage of the pre-driver using delay-matching generic gates for NAND and NOR functions. These gates also are used to bypass the clocks in AC-JTag and beacon modes. Impedance adjust is orthogonal to the level/EQ control.Previously, SST drivers have required such a high power, current variation and area penalty for level/EQ control that they are often unimplemented [2], thereby sacrificing compliance for a number of protocols. Two EQ design challenges for SST drivers are 1) mitigating the data-dependent supply current variation and 2) achieving enough granularity to meet exact specification requirements across different packages. Traditionally [3,4], an impedance-matched equalizing level is accomplished by replacing one PU/PD slice with its opposite at the full data rate. For example, one can achieve a level reduction of about 1.58dB by applying opposite data to one slice of a 12-slice output stage. However, this technique creates undesired data-dependent supply current fluctuations that increase with larger EQ settings. Furthermore, only 5 useful settings are available, (-1.58 to -...

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