Abnormal read disturb (RD) has been investigated in three-dimensional (3D) charge-trapping NAND flash memory. Similar to traditional 2D NAND, RD will cause more error bits right after programming. However, after short-time retention, it has weak effects on error bits; more importantly, after long-time retention, a part of error bits can be recovered. With special coding designs in chip characterizations and TCAD simulations, it is concluded that lateral charge migration could be dominant mechanism for abnormal RD, which can be utilized to prolong lifetime of 3D NAND-based memory system for cold storage applications.
Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (−30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells’ degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures.
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