IntroductionA high performance 0.20pm logic technology has been developed with six levels of planarized copper interconnects. 0.15pm transistors (Lg,,,=0.15+0.04pm) are optimized for 1.8V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects. Critical layer pitches for the technology are summarized in Table 1 and enable fabrication of 7.6pm2 6T SRAM cells.Isolation and Transistors CMP planarized shallow trenches with good electrical isolation down to n+/p+ spacings of 0.5pm were fabricated (Fig. 1). Dual gate 0.15pm transistors with 35A physical gate oxides (accumulation t,,=39A measured at Vg=+l .SV) were formed using super steep retrograde channels, shallow extensions and halos, relatively deep source/drain regions and 1 OOnm nitride spacers. CoSi, was selectively formed on the polysilicon gates and source/drain regions with a nominal sheet resistance of 9Wsq. Rapid thermal processing was utilized as much as possible throughout the flow to minimize transient enhanced dopant diffusion.Fig. 2 shows a typical SEM cross-section of a NMOS transistor with a gate length of 0.15pm. Well delineated shallow S/D extensions and the deeper S/D junctions are clearly observed. The saturation drive currents for nominal gate length NMOS and PMOS devices are shown in Fig. 3 . The nominal drive currents are 630pNpm for NMOS and 230pA/ym for PMOS at 1.8V. The off-state leakage currents of these devices are well below the worst case leakage specification of 2nA/pm. The drain induced barrier lowering (DIBL) measured on NMOS and PMOS devices is plotted as a function of Leff in Fig. 4. Good short channel characteristics are maintained down to effective channel lengths of O.1ym. The Vt roll-off for N and P devices in the linear and saturation regions are shown in Fig. 5. The Vt's are 0.44V and -0.46V for Nch and Pch respectively, at a gate length of 0.15pm and the associated subthreshold slopes are less than 90mv/dec. The use of nitrided gate oxides was investigated due to their superior hot carrier reliability. Fig. 6 compares the degradation under hot carrier stress of nitrided oxides to thermal oxides and highlights the improved reliability of NO-annealed oxides. Peak Gms comparable to those from thermal oxides were obtained (Fig. 7). A further advantage afforded by nitrided gate dielectrics is its superior boron blocking properties, Increasing the poly silicon doping in the P+ gate to reduce poly depletion resulted in only a 88mV Vt shift in nitrided oxides (Fig. 8) compared to a 300mV Vt shift in thermal oxides. A significant reduction in the inversion to, is achieved with the higher gate doping, resulting in improved device characteristics. NMOS transistor design focused on minimizing defect enhanced dopant re-distribution such as TED. To this end, the effect of different source/drain implant energies on NMOS transistor performance is shown in Fig. 9. The lower energy implant results in a significantl...
A Si/Mo/Ti trilayer structure which consists of a top, insulating Si film, a middle buffering Mo film, and a bottom Ti film is proposed for TiSi2 formation on n+ polysilicon. Since residual oxidants and impurity gases are effectively blocked by the Si layer, an N2‐normalflowing open tube with stringent environmental control is enough for the formation process above 750°C. The resultant sheet resistance of the silicided polysilicon is as low as 2% with good uniformity. Moreover, the resultant SiO2 thickness loss is reduced, and no metallic luster is shown on the oxide surface, eyen after the anneal at 800°C. The lateral formation of TiSi2 is found to be greatly suppressed in the anneal at 750°C for 15 min. Low resistivity, high environmental insensitivity, small oxide loss, and less lateral growth make the TiSi2 formation using the trilayer structure an attractive and promising method in many IC applications using silicides.
A selective epitaxial layer is grown in field regions rather than active device areas and is completely converted to thermal silicon-sioxide film to form the field oxide. This new technology results in a 'bird's beak'-free device. Called selective epitaxial-layer field oxidation (SELFOX), the technology offers several unique features: (i) uniform field oxide (1000 nm thickness) independent of the field area which can range from one micron to hundreds of microns, (ii)no bird's beak encroachment even for 1 ~m-thick field oxide, (iii) no dislocations in active device areas as small as 1 ~m. Reverse leakage ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 155.69.4.4 Downloaded on 2015-05-23 to IP Vol. 135, No. 10 ABSTRACT Fluorinated silicon nitride films were deposited by plasma-CVD from SiF4-N2-H2 or Si2F6-N2-H2 gas mixture. The deposition rate was increased by using the latter gas system, typically as high as 50 rim/rain, which was comparable to that of the conventional hydrogenated silicon nitride deposited from Sill4. The fluorinated silicon nitride exhibited (i) lower hydrogen content, (ii) higher stability against hydrogen outdiffusion, and (iii) higher thermal endurance. Successful applica-
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