This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm i 45nm and <40nm gate length transistor at EOT 1.95nm I 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1A and drive current is increased by 7%.Transistor Specification Table 1 lists the 65nm node transistor specification. Ion-Ioff and threshold roll-off are shown in Fig. 2-5 respectively. HS targets for desktop CPUiGPU application in which operating temperature is usually very high. Gate current is relaxed with high temperature operation in mind and therefore ultra-thin oxide 1.2nm EOT can be employed to enhance transistor performance. Strained Si is used for HS application where additional process complexityicost is acceptable for higher performance [4]. We apply a unique strained Si scheme that can improve NFET Idsat by 11 % and PFET Idsat by 27% without degrading short channel control and junction leakage ( Fig. 6) [5]. At nominal gate length, DlBL is below 130mVN and subthreshold swing is below 100mVidec for all transistors.Transistor gate length (Lg) and intrinsic CViI index are reduced by 20.30% compared to 90nm node [6] in order to meet the AC performance requirement in all three application segments of this 65nm CMOS technology. For CiLP HVT devices, the -2A reduction in oxide thickness has pushed the ON gate current very close to the room temperature sub-threshold leakage. Device hot-carrier, bias temperature stability and gate oxide time-dependent dielectric breakdown (TDDB) lifetime are verified to guarantee robust operation up to expected overdrive voltage. Fig. 7 shows 12A oxide TDDB and NBTl support operation up to 1 .OV Device Optimization Unlike previous generations, the scaling of oxide thickness and power supply are insufficient to achieve the aggressive Lg reduction. In 65nm node, channel length reduction must be achieved either by substantial overlap reduction, reducing LDD junction depth, or both. Offset spacer and thermal cycle reduction are the two most promising approaches. Although the use of offset spacer can improve short channel control without the need of scaling LDD junction depth, the drain current variation is higher due to offset spacer CD fluctuation. Thermal cycle reduction is more promising as it does improve the intrinsic short channel 92 0-7803-8289-7/04/$20.00 D 2004 IEEE behavior including effective L and reverse short channel effect (RSCE), and it is relatively easier to manufacture. In 65nm generation, we have explored the device design space at reduced thermal cycle.By reducing spike RTA by 30C, there is remarkable lOnm improvement in DIBL-Lg behavior (Fig. ...
For both FSG or C-doped oxide samples containing copper (Cu) metallization, Cu was often dissolved during wet delineation steps for cross-sectional SEM samples. Length effect was the important factor for avoiding Cu dissolution during wet delineation process. This paper presents practical methods to prevent Cu damage for FIB cross-sectional and mechanical polished SEM samples.
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