A high-speed Huffman decoder for real-time video applications has been developed. The most dominant part of MPEG video bit-stream, DCT coefficients, can be decoded in 4 cycles or less using the proposed circuit, while the table size is smaller than the case of the conventional binary search. Bit-streams can be decoded up to 6 bit/cycle, which enables 162Mbit/s decoding at 27MHz.
A VLSI chip set capable of real-time MPEG (Moving Picture Experts Group) video encoding/decoding has been developed. It is composed of an inter-frame prediction chip, a transform and quantization chip, and a variable length coding chip. To make the chip set more cost effective, the MPEG algorithms are first partitioned into three blocks on the basis of their characteristics. Individual chip architectures are designed with the use of programmable DSP and application specific array approaches. A hierarchical data transmission method is introduced for use among the chips and frame memories. By using these three chips, an MPEG video encoder can compress a 30 frames/sec image sequence of 352 pels x 240 lines. A decoder can be constructed with two chips for the same sequence.
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