A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking

Mizuno, Masayuki; Ooi, Y.; Hayashi, Naoya; Goto, J.; Hozumi, M.; Furuta, K.; Shibayama, A.; Nakazawa, Yasuhiro; Ohnishi, O.; Zhu, Shuyu; Yokoyama, Yutaka; Katayama, Y.; Takano, H.; Miki, N.; Senda, Yuzo; Tamitani, I.; Yamashina, M.

doi:10.1109/4.641704

Cited by 58 publications

(6 citation statements)

References 8 publications

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“…In this review, FSBM [11]- [17] and fast block matching algorithm [18]- [25] based VLSI architectures derived from inter-type and intra-type systolic mapping with 1-D, 2-D, and tree structures were reviewed with detailed comparison. Six aspects including gate count, clock frequency, hardware utilization, memory bandwidth, memory bit-width, and sum of absolute difference (SAD) latency were used as the comparison criteria.…”

Section: A Challengesmentioning

confidence: 99%

A Hardware-Efficient Multi-Resolution Block Matching Algorithm and its VLSI Architecture for High Definition MPEG-Like Video Encoders

Yin

Jia

Qi³

et al. 2010

IEEE Trans. Circuits Syst. Video Technol.

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High throughput, heavy bandwidth requirement, huge on-chip memory consumption, and complex data flow control are major challenges in high definition integer motion estimation hardware implementation. This paper proposes an efficient very large scale integration architecture for integer multi-resolution motion estimation based on optimized algorithm. There are three major contributions in this paper. First, this paper proposes a hardware friendly multi-resolution motion estimation algorithm well-suited for high definition video encoder. Second, parallel processing element (PE) array structure is proposed to implement three-level hierarchical motion estimation, only 256 PEs are enough for one reference frame real-time high definition motion estimation by efficient PE reuse. Third, efficient on-chip reference pixel buffer sharing mechanism between integer and fractional motion estimation is proposed with almost 50% SRAM saving and memory bandwidth reduction. The proposed multi-resolution motion estimation algorithm reached a good balance between complexity and performance with rate distortion optimized variable block size motion estimation support. Also, we have achieved moderate logic circuit and on-chip SRAM consumption. The proposed architecture is well-suited for all MPEG-like video coding standards such as H.264, audio video coding standard, and VC-1.Index Terms-Architecture, audio video coding standard (AVS), H.264, multi-resolution motion estimation, very large scale integration (VLSI), video coding.

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Section: A Challengesmentioning

confidence: 99%

A Hardware-Efficient Multi-Resolution Block Matching Algorithm and its VLSI Architecture for High Definition MPEG-Like Video Encoders

Yin

Jia

Qi³

et al. 2010

IEEE Trans. Circuits Syst. Video Technol.

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“…Approximate algorithms, such as the three-step search block-matching algorithm [2] can be used instead of the full-search block matching algorithm. A smaller search window can be used to reduce the computational load and power consumption [3]. Another method is using the bit-truncation technique, in which the bit precision is adjusted such that the bit-width, and thus the hardware cost of the ME modules are minimized with the performance meeting the specification.…”

Section: Introductionmentioning

confidence: 99%

Low-power VLSI design for motion estimation using adaptive pixel truncation

Tsui

Chan³

et al. 2000

IEEE Trans. Circuits Syst. Video Technol.

116

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Power consumption is very critical for portable video applications such as portable videophone and digital camcorder. Motion estimation (ME) in the video encoder requires a huge amount of computation, and hence consumes the largest portion of power. In this paper, we propose a novel method of reducing power consumption of the ME by adaptively changing the pixel resolution during the computation of the motion vector. The pixel resolution is changed by masking or truncating the least significant bits of the pixel data, which is governed by the bit-rate control mechanism. Experimental results show that on average more than 4 bits can be truncated without significantly affecting the picture quality. This results in more than 60% reduction in power consumption.

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“…4, and its main features are summarized in Table II. It should be emphasized that comparing to an existing single chip MPEG-2 MP@ML encoder [3] which has approximately the same target picture size, and was also fabricated in a 0.35 µm 3LM process, our wavelet encoder successfully reduces power consumption from 1.5 W to 210 mW, and chip area from 12.45×12.45 mm 2 to 4.93×4.93 mm 2 . The proposed implementation is capable of encoding one 720×480 4:2:0 YCbCr color frame within approximately 1,050,000 clock cycles, and hence a frame rate of 30 fps can be achieved by the clock frequency of 33.0 MHz.…”

Section: Vlsi Implementationmentioning

confidence: 99%

Realtime wavelet video coder based on reduced memory accessing

Omaki

Dong

Miki

et al. 2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

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Abstract-In this paper, the VLSI implementation of a realtime EZW video coder is presented. The proposed architecture adopts a modified 2-D DWT subband decomposition scheme, with the purpose of reducing the transposition memory requirements of 2-D DWT. In addition, through the use of a parallelized partial zerotree EZW scheme, temporary buffer requirements between the DWT and EZW modules are also reduced. The video encoder is integrated in a 0.35 um 3LM chip by using 341 K transistors on a 4.93×4.93 mm 2 die.

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A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking

Cited by 58 publications

References 8 publications

A Hardware-Efficient Multi-Resolution Block Matching Algorithm and its VLSI Architecture for High Definition MPEG-Like Video Encoders

A Hardware-Efficient Multi-Resolution Block Matching Algorithm and its VLSI Architecture for High Definition MPEG-Like Video Encoders

Low-power VLSI design for motion estimation using adaptive pixel truncation

Realtime wavelet video coder based on reduced memory accessing

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