An encoder/decoder chip set for the MPEG video standard

Abstract

A VLSI chip set capable of real-time MPEG (Moving Picture Experts Group) video encoding/decoding has been developed. It is composed of an inter-frame prediction chip, a transform and quantization chip, and a variable length coding chip. To make the chip set more cost effective, the MPEG algorithms are first partitioned into three blocks on the basis of their characteristics. Individual chip architectures are designed with the use of programmable DSP and application specific array approaches. A hierarchical data transmission method is introduced for use among the chips and frame memories. By using these three chips, an MPEG video encoder can compress a 30 frames/sec image sequence of 352 pels x 240 lines. A decoder can be constructed with two chips for the same sequence.

A 162 Mbit/s variable length decoding circuit using an adaptive tree search technique

“…9). The device is a member of real-time MPEG CODEC chip set which operates at 27MHz (7). In this situation, the device can achieve 162MbiVs bit-stream decoding.…”

A Simd Dsp For Real-time Mpeg Video Encoding And Decodiing

“…An MPEG video encoder chip set approach has been proposed by the authors in [5] to meet above requirements. In the approach, the MPEG video algorithm is partitioned into three core blocks (COBS) based on its processing characteristics.…”

VLSI architecture for motion estimation using the block-matching algorithm

“…These dedicated solutions were based on a chip-set of ASICs [8][9][10]. However, research activity in this direction has decreased because there are two drawbacks: a long design time is required and the systems are not flexible to adaptation to changes in the standards.…”