We present GaN-based high electron mobility transistors (HEMTs) with a 2-nm-thin InAlN/AlN barrier capped with highly doped n ++ GaN. Selective etching of the cap layer results in a well-controllable ultrathin barrier enhancement-mode device with a threshold voltage of +0.7 V. The n ++ GaN layer provides a 290-Ω/ sheet resistance in the HEMT access region and eliminates current dispersion measured by pulsed IV without requiring additional surface passivation. Devices with a gate length of 0.5-µm exhibit maximum drain current of 800 mA/mm, maximum transconductance of 400 mS/mm, and current cutoff frequency f T of 33.7 GHz. In addition, we demonstrate depletionmode devices on the same wafer, opening up perspectives for reproducible high-performance InAlN-based digital integrated circuits.Index Terms-Enhancement mode (E-mode), gate recess, high electron mobility transistor (HEMT), InAlN/GaN heterostructure. I N THE LAST decade, high electron mobility transistors (HEMTs) based on GaN have demonstrated excellent radiofrequency (RF) power switching and high-frequency performances due to its wide bandgap, large critical electric field, and high lattice-based polarization. While most results were shown on AlGaN barrier devices [1], recently, also InAlN/GaN-based HEMTs have demonstrated high-power and high-temperature performance, constituting a new class of lattice-matched stressfree thermally and chemically stable devices with enhanced polarization [2], [3]. This polarization, which is based on the polar nature of III-N materials, causes the usual depletion-mode (Dmode) operation of such devices. In the past, a lot of research has been carried out to increase the threshold voltage of HEMT devices toward enhancement-mode (E-mode) operation in order to reduce circuit design complexity, include device failsafe, or Manuscript even realize digital integrated circuits. On the one hand, several approaches were developed to raise the conduction band below the gate. By using p-doped GaN [4] or InGaN [5] interlayers, the transfer characteristic could be shifted to the normally off regime, but it reduced the device performance due to the limitation of acceptable forward bias. A similar approach was done using F+ ion implantation in order to incorporate positive charges below the gate [6]. The increased barrier also reduces the gate leakage current, allowing gate biasing up to 4 V [7]. However, such techniques may not be thermally stable above 500 • C, which counters the desirable property of GaN-based devices to withstand harsh environments. On the other hand, high-performing E-mode devices were achieved by reducing the barrier thickness below the gate [7], [8], thus decreasing the required voltage swing to pinch off the device. Nevertheless, high controllability and, consequently, good reproducibility of such a process are hard to achieve.In this letter, we report on a novel device structure for E-mode and D-mode HEMTs based on a 1-nm lattice-matched InAlN barrier with an additional 1-nm AlN interlayer. Using an only 2-nm-thin ...