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Vertical GaN-based light-emitting diodes (LEDs) were fabricated with a Si substrate using the wafer-bonding technique. Lapping and dry-etching processes were performed for thinning the sapphire substrate instead of removing this substrate using the laser lift-off technique and the thinning process associated with the wafer-bonding technique to feature LEDs with a sapphire-face-up structure and vertical conduction property. Compared with conventional lateral GaN/sapphire-based LEDs, GaN/Si-based vertical LEDs exhibit higher light output power and less power degradation at a high driving current, which could be attributed to the fact that vertical LEDs behave in a manner similar to flip-chip GaN/sapphire LEDs with excellent heat conduction. In addition, with an injection current of 350 mA, the output power (or forward voltage) of fabricated vertical LEDs can be enhanced (or reduced) by a magnitude of 60% (or 5%) compared with conventional GaN/sapphire-based LEDs.

We present an efficient vertical InGaN light-emitting diode (LED) in which the proposed vertical LEDs were fabricated with patterned sapphire substrates (PSS) using thinning techniques. After the thinning of sapphire substrate, selective dry etching process was performed on the remainder sapphire layer to expose the n-GaN contact layer instead of removing the sapphire substrate using the laser lift-off technique. These processes feature the LEDs with a sapphire-face-up structure and vertical conduction property. The PSS was adopted as a growth substrate to mitigate the light-guided effect, and thereby increase the light-extraction efficiency. Compared with conventional lateral GaN LEDs grown on PSS, the proposed vertical LEDs exhibit a higher light output power and less power degradation at a high driving current. This could be attributed to the fact that the vertical LEDs behave in a manner similar to flip-chip GaN/sapphire LEDs with excellent heat conduction.

The thick-well InGaN/GaN short period multiple quantum well solar cells (SCs) with H in the GaN cap layer exhibits an improved open-circuit voltage, fill factor, and conversion efficiency ( ) compared with those of SCs without the ramped H in the GaN cap layer. The of the SC with the ramped H in the GaN cap layer (0.77%) shows a 67.4% improvement compared with that of the SC without the ramped H (0.46%). Furthermore, the of SC with patterned sapphire substrate (PSS) (1.36%) indicates a 76.6% improvement compared with that of SC without PSS (0.77%). Index Terms-GaN-based solar cells (SCs), short-period (SP) InGaN/GaN multiple-quantum well (MQW).

Fundamental understanding of the generation and multiplication of basal plane dislocations (BPDs) in PVT-grown 4H-SiC crystals is critical for design of growth strategies to control their densities during PVT growth of 4H-SiC crystals. Direct observation of thermal gradient induced motion of basal plane dislocations by in-situ synchrotron X-ray topography imaging of PVT-grown 4H-SiC wafers subject to high temperature treatment has provided an opportunity to analyze the movement of dislocations. Dislocations with Burgers vector along the off-cut [11-20] direction were found to be the only dislocations involved in deformation during heat treatment and the segments of dislocations used for velocity measurements were found to be either pure screw comprised of both Si- and C- core partials or 60° dislocations comprised of purely Si cores. Using the kink-diffusion model, the activation energies for dislocation motion have been estimated from the velocity data for each of these dislocation types and found to be 2.21 eV for 60° and 3.28 eV for pure screw segments, respectively. These values are in good agreement with the macroscopic studies of yielding of semiconductor crystals during high temperature compression and indentation experiments. Quantitative expression of the temperature dependent critical resolved shear stress required for dislocation motion has been derived from this analysis.

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Dislocation behavior during homo-epitaxy of 4H-SiC on offcut substrates by Chemical Vapor Deposition (CVD) has been studied using Synchrotron X-ray Topography and KOH etching. Studies carried out before and after epilayer growth have revealed that, in some cases, short, edge oriented segments of basal plane dislocation (BPD) inside the substrate can be drawn towards the interface producing screw oriented segments intersecting the growth surface. In other cases, BPD half-loops attached to the substrate surface are forced to glide into the epilayer producing similar screw oriented surface intersections. These screw segments subsequently produce interfacial dislocations (IDs) and half-loop arrays (HLAs). We also report on the formation of IDs and HLAs generated from: (a) surface sources of BPDs; (b) micropipes; (c) 3C inclusions; and (d) substrate/epilayer interface scratches. The HLAs are known to result in Shockley fault expansion within the epilayer which results in forward voltage drop and device failure.

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