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Spin-transfer torque random access memory (STT-RAM) has received increasing attention because of its attractive features: good scalability, zero standby power, non-volatility and radiation hardness. The use of STT-RAM technology in the last level on-chip caches has been proposed as it minimizes cache leakage power with technology scaling down. Furthermore, the cell area of STT-RAM is only 1/9 ∼ 1/3 that of SRAM. This allows for a much larger cache with the same die footprint, improving overall system performance through reducing cache misses. However, deploying STT-RAM technology in L1 caches is challenging because of the long and power-consuming write operations. In this paper, we propose both L1 and lower level cache designs that use STT-RAM. In particular, our designs use STT-RAM cells with various data retention time and write performances, made possible by different magnetic tunneling junction (MTJ) designs. For the fast STT-RAM bits with reduced data retention time, a counter controlled dynamic refresh scheme is proposed to maintain the data validity. Our dynamic scheme saves more than 80% refresh energy compared to the simple refresh scheme proposed in previous works. A L1 cache built with ultra low retention STT-RAM coupled with our proposed dynamic refresh scheme can achieve 9.2% in performance improvement, and saves up to 30% of the total energy when compared to one that uses traditional SRAM. For lower level caches with relative large cache capacity, we propose a data migration scheme that moves data between portions of the cache with different retention characteristics so as to maximize the performance and power benefits. Our experiments show that on the average, our proposed multi retention level STT-RAM cache reduces 30 ∼ 70% of the total energy compared to

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Magnetization reversals through the formation of a vortex state and the rotation of an onion state are two processes with comparable probabilities for symmetric magnetic nanorings with a radius of about 50 nanometers. This magnetic bistability is the manifestation of the competition between the exchange energy and the magnetostatic energy in nanomagnets. The relative probability of the two processes in symmetric nanorings is dictated by the ring geometry and cannot be altered after fabrication. In this work, we report a novel type of nanorings--asymmetric nanorings. By tuning the asymmetry, we can control the fraction of the vortex formation process from about 40% to nearly 100% by utilizing the direction of the external magnetic field. The observed results have been accounted for by the dependence of the domain-wall energy on the local cross-section area for which we have provided theoretical calculations.

In conclusion, we have demonstrated a hybrid-memory device where information can be introduced optically and can be extracted or erased electrically. We expect much improved performance, in terms of retention, stability, and operating voltages upon introducing intentional electron-trapping centers in dilute proportions in the semiconducting-polymer matrix, along with optimization of geometrical parameters. ExperimentalThe top-contact geometry, as shown in Figure 1a, was used to fabricate the polymer field-effect transistor devices based on poly(3-hexylthiophene) (P3HT) [7]. Regioregular P3HT was obtained from Aldrich Inc., and was re-purified using standard procedures (re-precipitation method). Our samples and devices were handled in a glove box (MBraun, Inc.), and stringent procedures were observed to ensure the quality of the devices. A transparent water-soluble dielectric (polyvinyl alcohol, e » 8) layer with a thickness of 0.5 lm was spincoated on top of an aluminum-coated glass substrate. The dielectric surface was then treated using standard established procedures using hexamethyldisilazane. A layer of regioregular P3HT (thickness » 150 nm) was spin-coated (1500 rpm) from chloroform solution on the insulator under an inert atmosphere, followed by a thermal treatment under vacuum at 60 C for 24 h. The drain and source electrodes with a separation of 25±40 lm (L) and width of 2 mm (W) were deposited by thermal evaporation of gold using a shadow mask. All the experiments were performed under vacuum (10 ±1 Pa).