45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell

Lin, Chrong Jung; Kang, Sangmo; Wang, Y.J.; Lee, K.; Zhu, Xiwei; Chen, W.C.; Li, X.; Hsu, W.N.; Kao, Ya-Chen; Liu, M.T.; Lin, Yung-Hsiang; Nowak, Matt; Yu, Nick; Tran, L.C.

doi:10.1109/iedm.2009.5424368

Cited by 216 publications

(140 citation statements)

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“…The energy required to read the all of the bit cells in a cache line is around 90pJ without ECC, based on figures reported in [12], but can be decreased to around 40pJ when c = 6 and t f = 10ms. Consequently, the total energy to read a cache line remains the same, despite the decoder overhead.…”

Section: A Example Stt-mram Cachementioning

confidence: 99%

“…The effect of multibit correction is evaluated using a 45nm in-plane 1T1MTJ STT-MRAM design based on [10], [12]. For this analysis, a 32Mb last-level cache with three possible refresh periods is utilized, and any error correction is done using 64B line-level encoding.…”

Section: A Example Stt-mram Cachementioning

confidence: 99%

“…In 1T1MTJ designs, the cell area is dominated by the size of the access transistor: for example, a reference 45nm design [12] uses a size that is 6× wider than the minimum feature size. Better integration densities for memory cells can be achieved by using smaller memory cells, but there is a tradeoff between cell area and error rate, both of which are related to the thermal stability of the free layer.…”

mentioning

confidence: 99%

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Improving STT-MRAM density through multibit error correction

Bel

Kim

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-STT-MRAMs are prone to data corruption due to inadvertent bit flips. Traditional methods enhance robustness at the cost of area/energy by using larger cell sizes to improve the thermal stability of the MTJ cells. This paper employs multibit error correction with DRAM-style refreshing to mitigate errors and provides a methodology for determining the optimal level of correction. A detailed analysis demonstrates that the reduction in nonvolatility requirements afforded by strong error correction translates to significantly lower area for the memory array compared to simpler ECC schemes, even when accounting for the increased overhead of error correction.

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Section: A Example Stt-mram Cachementioning

confidence: 99%

Section: A Example Stt-mram Cachementioning

confidence: 99%

mentioning

confidence: 99%

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Improving STT-MRAM density through multibit error correction

Bel

Kim

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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“…Prominent examples for such devices are spin-transfer torque magnetic random-access memories (STT MRAM) [1,2,3] and spin-torque oscillators (STO) that serve as field generators for microwave assisted recording of hard-disk drives [4,5].…”

Section: Introductionmentioning

confidence: 99%

Fieldlike and Dampinglike Spin-Transfer Torque in Magnetic Multilayers

et al. 2017

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We investigate the spin-transfer torque in a magnetic multilayer structure by means of a spin-diffusion model. The torque in the considered system, consisting of two magnetic layers separated by a conducting layer, is caused by a perpendicular-to-plane current. We compute the strength of the field-like and the damping-like torque for different material parameters and geometries. Our studies suggest that the field-like torque highly depends on the exchange coupling strength of the itinerant electrons with the magnetization both in the pinned and the free layer. While a low coupling leads to very high field-like torques, a high coupling leads to low or even negative field-like torques. The dependence of the different torque terms on system parameters is considered very important for the development of applications such as STT MRAM and spin-torque oscillators.

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“…lay and energy scaling characteristics [24]. Multi-megabit array prototypes at competitive technology nodes (e.g., 45nm, 65nm) have already been demonstrated [56,33], and the ITRS projects STT-MRAM to be in production by 2013 [24]. In STT-MRAM, information is stored by modulating the magnetoresistance of a thin film stack called a magnetic tunnel junction (MTJ).…”

Section: Resistive Memory Technologiesmentioning

confidence: 99%

A resistive TCAM accelerator for data-intensive computing

Guo

Bai

et al. 2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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Power dissipation and o↵-chip bandwidth restrictions are critical challenges that limit microprocessor performance. Ternary content addressable memories (TCAM) hold the potential to address both problems in the context of a wide range of data-intensive workloads that benefit from associative search capability. Power dissipation is reduced by eliminating instruction processing and data movement overheads present in a purely RAM based system. Bandwidth demand is lowered by processing data directly on the TCAM chip, thereby decreasing o↵-chip tra c. Unfortunately, CMOSbased TCAM implementations are severely power-and arealimited, which restricts the capacity of commercial products to a few megabytes, and confines their use to niche networking applications.This paper explores a novel resistive TCAM cell and array architecture that has the potential to scale TCAM capacity from megabytes to gigabytes. High-density resistive TCAM chips are organized into a DDR3-compatible DIMM, and are accessed through a software library with zero modifications to the processor or the motherboard. On applications that do not benefit from associative search, the TCAM DIMM is configured to provide ordinary RAM functionality. By tightly integrating TCAM with conventional virtual memory, and by allowing a large fraction of the physical address space to be made content-addressable on demand, the proposed memory system improves average performance by 4⇥ and average energy consumption by 10⇥ on a set of evaluated data-intensive applications.

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45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell

Cited by 216 publications

References 0 publications

Improving STT-MRAM density through multibit error correction

Improving STT-MRAM density through multibit error correction

Fieldlike and Dampinglike Spin-Transfer Torque in Magnetic Multilayers

A resistive TCAM accelerator for data-intensive computing

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