Fast, convenient, and highly sensitive detection of antibiotic is essential to avoid its overuse and the possible harm. Owing to enrichment effect and antifouling ability of ultrasmall nanochannels, the vertically ordered mesoporous silica nanochannel film (VMSF) has great potential in the development of the facile electrochemiluminescence (ECL) sensor for direct and sensitive analysis of antibiotics in complex samples. In this study, we demonstrated a flexible ECL sensor based on a cost-effective electrode covered with a VMSF for sensitive detection of clindamycin. Polyethylene terephthalate coated with indium tin oxide (PET-ITO) is applied as a flexible electrode to grow VMSF using the electrochemically assisted self-assembly (EASA) method. The negatively charged VMSF nanochannels exhibit significant enrichment toward the commonly used cationic ECL luminophores, tris(2,2-bipyridyl) dichlororuthenium (II) (Ru (bpy)32+). Using the enhanced ECL of Ru (bpy)32+ by clindamycin, the developed VMSF/PET-ITO sensor can sensitively detect clindamycin. The responses were linear in the concentration range of 10 nM–25 μM and in the concentration range of 25–70 μM. Owing to the nanoscale thickness of the VMSF and the high coupling stability with the electrode substrate, the developed flexible VMSF/PET-ITO sensor exhibits high signal stability during the continuous bending process. Considering high antifouling characteristic of the VMSF, direct analysis of clindamycin in a real biological sample, human serum, is realized.

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In this paper, we propose a new quick and effective legitimate skew clock routing with buffer insertion algorithm. We analyze the optimal buffer position in the clock path, and conclude the sufficient condition and heuristic condition for buffer insertion in clock net. During the routing process, this algorithm integrates buffer insertion and node merging together, and performs them in parallel. Compared with the method of buffer insertion after zero skew clock routing, our method improves the maximal clock delay by at least 48%. Compared with legitimate skew clock routing algorithm with no buffer, this algorithm further decreases the total wire length and gets reductions from 42 to 82% in maximal clock delay. The experimental results show that our algorithm is quick and effective.

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