The high power microwave (HPM) damage effect on the AlGaAs/InGaAs pseudomorphic high electron mobility transistor (pHEMT) is studied by simulation and experiments. Simulated results suggest that the HPM damage to pHEMT is due to device burn-out caused by the emerging current path and strong electric field beneath the gate. Besides, the results demonstrate that the damage power threshold decreases but the energy threshold slightly increases with the increase of pulse-width, indicating that HPM with longer pulse-width requires lower power density but more energy to cause the damage to pHEMT. The empirical formulas are proposed to describe the pulse-width dependence. Then the experimental data validate the pulse-width dependence and verify that the proposed formula P = 55τ −0.06 is capable of quickly and accurately estimating the HPM damage susceptibility of pHEMT. Finally the interior observation of damaged samples by scanning electron microscopy (SEM) illustrates that the failure mechanism of the HPM damage to pHEMT is indeed device burn-out and the location beneath the gate near the source side is most susceptible to burn-out, which is in accordance with the simulated results.
The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave (HPM) is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS inverters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.
A study of the internal damage process and mechanism of the typical n+-p-n-n+ structure bipolar transistor induced by the intense electromagnetic pulse (EMP) is carried out in this paper from the variation analysis of the distribution of the electric field,the current density and the temperature. Research shows that the damage position of the bipolar transistor is different with the different magnitude of the injecting voltage,when the magnitude of the injecting voltage is low the damage will appear firstly near the collector region under the center of the emitter region,and when the magnitude of the injecting voltage is sufficiently high the damage will appear firstly at the edge of the base near the emitter due to the breakdown of the PIN structure composed of the base-epitaxial layer-collector. Adopting the data analysis software,the relation equation between the device damage power P and the pulse width T under different injecting voltage is obtained. Owing to the variety of the device damage energy,it is demonstrated that the empirical formulas of the intense electromagnetic pulse P=AT-1 (A is a constant) is modified to P=AT-1.4 for the bipolar transistor.
We derive analytical models of the excess carrier density distribution and the HPM (high-power microwave) upset susceptibility with dependence of pulse-width, which are validated by the simulated results and experimental data. Mechanism analysis and model derivation verify that the excess carriers dominate the current amplification process of the latch-up. Our results reveal that the excess carrier density distribution in P-substrate behaves as pulse-width dependence. The HPM upset voltage threshold V p decreases with the incremental pulsewidth, while there is an inflection point which is caused because the excess carrier accumulation in the P-substrate will be suppressed over time. For the first time, the physical essence of the HPM pulse-width upset effect is proposed to be the excess carrier accumulation effect. Validation concludes that the V p model is capable of giving a reliable and accurate prediction to the HPM upset susceptibility of a CMOS inverter, which simultaneously considers technology information, ambient temperature, and layout parameters. From the model, the layout parameter L B has been demonstrated to have a significant impact on the pulse-width upset effect: a CMOS inverter with minor L B is more susceptible to HPM, which enables us to put forward hardening measures for inverters that are immune from the HPM upset.
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